Tetsuo Endoh

This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), discussing each RAM's features and its applications. Then current status of spintronics developments including not only STT-MRAM but also nonvolatile logic LSI is described, which are particularly suitable for working memory applications.

In order to overcome the limitation of cell area of 4F/sup 2/ per bit in conventional NAND flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F/sup 2//N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less

Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit torque (SOT), and electric field (E-field) effect on magnetic anisotropy.

An accurate model and a numerical analysis of the subbreakdown phenomenon due to band-to-band tunneling in a thin-gate-oxide n-MOSFET is described. Results calculated by means of this model agree well with experimental results. This model provides a good understanding of the subbreakdown phenomenon. Furthermore, it shows how to design the distribution of impurity density in the drain region in order to suppress the subbreakdown current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:

In last decade, since high performance MTJ using CoFeB/MgO-based interfacial perpendicular magnetic anisotropy (IPMA) is utilized, STT-MRAM technology has rapidly progressed and mass-production of STT-MRAM has already started in the semiconductor companies. However, for further expansion of MRAM applications and markets, higher reliability, larger capacity or speed are required. In this invited paper, we describe our recent progresses in STT-/SOT-MRAM fabricated under developed 300mm integration

According to the International Roadmap for Devices and Systems, gate-all-around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs) will become the main devices in integrated circuits over the next few decades. However, both vertical and lateral GAA-MOSFETs currently face two issues: large variance in sub-10-nm devices and challenges in integration. In particular, vertical GAA-MOSFETs have an asymmetric source/drain structure that is different from that of all other MOSFETs, resul

The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promi

The incubation (transit) time of the perpendicular magnetic tunnel junction (MTJ) is found shorter (longer) than the in-plane MTJ. By making use of the incubation time, a new concept is proposed for MTJ/CMOS hybrid circuits that operate as fast as CMOS circuits without operation power overhead and with negligible MTJ switching error. A nonvolatile latch based on the concept is fabricated in 90nm technology to demonstrate 600MHz stable operation.