[論文レビュー] Closing the Gap Between Float and Posit Hardware Efficiency

Aditya Anirudh Jonnalagadda, Rishi Thotli+1 more|arXiv (Cornell University)|Mar 2, 2026

Numerical Methods and Algorithms被引用数 0

ひとこと要約

本論文は b-posit（境界 regime posit 形式）を提案し、デコーダ/エンコーダアーキテクチャを提示する。これらはハードウェアコストを大幅に削減しつつ、IEEE 浮動小数点よりも Posit の利点を維持し、特に高精度で優位性を示す。

ABSTRACT

The b-posit, or bounded posit, is a variation of the posit format designed for high performance computing (HPC) and AI applications. Unlike traditional floating-point formats (floats), posits use variable-length fields for exponent scaling and significand, providing better efficiency for the same bit width. However, this flexibility introduces high worst-case overhead in decode-encode logic, exceeding the cost of handling subnormals for floats. To address this, the b-posit restricts the regime field to a 6-bit limit, reducing variability in regime and fraction sizes. With an exponent size eS of 5 bits, the dynamic range is $2^{-192}$ to $2^{192}$ (about $10^{-58}$ to $10^{58}$) and the quire size is 800 bits, for any precision $n>12$. This constraint improves numerical properties and simplifies hardware implementation by allowing decode-encode operations with basic multiplexers. Our 32-bit b-posit decoder circuits achieve significant improvements: 79 percent less power consumption, 71 percent smaller area, and 60 percent reduced latency compared to standard posit decoders. The 32-bit b-posit encoder shows 68 percent lower power usage, 46 percent less area, and 44 percent shorter delay. The proposed b-posit hardware exhibits superior scalability with increasing bit widths, outperforming standard posit hardware at higher precisions, with even greater advantages at 64-bit. Notably, the b-posit decode-encode hardware matches or exceeds IEEE compliant 32-bit floating-point performance, offering faster and smaller area implementation, with slight increase in worst-case power due to higher speed. The b-posit hardware design provides the clean mathematical behavior and higher accuracy of posits versus IEEE floats without the power, area, or latency costs observed for the Posit Standard (2022). We believe the b-posit should influence future standard revisions.

研究の動機と目的

• Motivate the need to reduce the hardware cost of decode-encode in standard posits for HPC/AI workloads.
• Propose a bounded-regime posit (b-posit) with a maximum regime size to simplify hardware and improve parallelism.
• Design and implement fully parameterizable b-posit decoder and encoder circuits.
• Demonstrate scalability and efficiency of b-posit hardware across multiple precisions.
• Compare b-posit performance against standard posits and IEEE 754 floating-point implementations.

提案手法

• Define the b-posit format as ⟨N, rS, eS⟩ with rS=6 and eS chosen to balance dynamic range and precision.
• Develop a two-stage decode that begins with regime size identification using a five-bit prefix and a one-hot encoding for regime sizes.
• Implement a parallel multiplexer-based packing for exponent and regime fields to enable constant-ish latency across precisions.
• Create a b-posit encoder that uses an XOR-based regime-size determination and a small binary decoder to select packing configurations.
• Analyze hardware complexity and show that b-posit decoding/encoding latency remains nearly constant while area and power scale with precision.
• Compare against standard posit and IEEE-float decode-encode paths, highlighting improvements in area, power, and latency.

実験結果

リサーチクエスチョン

• RQ1 Can bounding the regime size to rS=6 reduce decode-encode complexity without severely compromising dynamic range or accuracy?
• RQ2 How does b-posit decoding/encoding latency scale with increasing precision (e.g., 16-, 32-, 64-bit) compared to standard posits and IEEE floats?
• RQ3 Do b-posit circuits achieve hardware efficiency competitive with IEEE 32-bit floating-point while preserving Posit’s accuracy properties?
• RQ4 What is the impact of eS choice in conjunction with rS on dynamic range and numerical properties for HPC/AI workloads?

主な発見

• 32-bit b-posit decoder consumes 79% less power, 71% smaller area, and 60% lower latency than standard posit decoders.
• 32-bit b-posit encoder uses 68% lower power, 46% less area, and 44% shorter delay than standard posit encoders.
• b-posit hardware shows superior scalability with increasing bit widths, outperforming standard posit hardware at higher precisions.
• The b-posit decode-encode pipeline matches or exceeds performance of IEEE 32-bit floating-point in speed and area, with a slight increase in worst-case power due to higher speed.
• The bounded-regime design enables parallel decoding with basic multiplexers, reducing hardware complexity compared to full-width regime posits.
• b-posit’s bounded dynamic range and tapered accuracy provide robust numerical properties useful for AI and HPC workloads.