[論文レビュー] Modular decoding: parallelizable real-time decoding for quantum computers

Héctor Bombín, Christopher Dawson+4 more|arXiv (Cornell University)|Mar 8, 2023

Quantum Computing Algorithms and Architecture被引用数 9

ひとこと要約

本論文は edge-vertex decomposition を介して、故障耐性量子コンピュータのリアルタイムかつ並列化可能なデコードを可能にするモジュラー・デコードを導入する。 buffering 条件が故障距離を保存することを証明し、Monte Carlo simulations を用いた実証により、オフラインデコードの正確さを維持するには buffers が必要かつ十分であることを示し、巨大規模の magic-state distillation を含む。

ABSTRACT

Universal fault-tolerant quantum computation will require real-time decoding algorithms capable of quickly extracting logical outcomes from the stream of data generated by noisy quantum hardware. We propose modular decoding, an approach capable of addressing this challenge with minimal additional communication and without sacrificing decoding accuracy. We introduce the edge-vertex decomposition, a concrete instance of modular decoding for lattice-surgery style fault-tolerant blocks which is remarkably effective. This decomposition of the global decoding problem into sub-tasks mirrors the logical-block-network structure of a fault-tolerant quantum circuit. We identify the buffering condition as a key requirement controlling decoder quality; it demands a sufficiently large separation (buffer) between a correction committed by a decoding sub-task and the data unavailable to it. We prove that the fault distance of the protocol is preserved if the buffering condition is satisfied. Finally, we implement edge-vertex modular decoding and apply it on a variety of quantum circuits, including the Clifford component of the 15-to-1 magic-state distillation protocol. Monte Carlo simulations on a range of buffer sizes provide quantitative evidence that buffers are both necessary and sufficient to guarantee decoder accuracy. Our results show that modular decoding meets all the practical requirements necessary to support real-world fault-tolerant quantum computers.

研究の動機と目的

• リアルタイムデコードのニーズを fault-tolerant quantum computation で addressingする。
• Decompose global decoding into parallel sub-tasks mirroring fault-tolerant circuit structure.
• Introduce buffering as a key condition to preserve decoding accuracy.
• Prove a soundness theorem ensuring modular decoding matches offline decoding under buffering.
• Demonstrate practicality through numerical simulations on complex logical block networks, including 15-to-1 magic-state distillation.

提案手法

• Define modular decoding and edge-vertex decomposition tailored to lattice-surgery style fault tolerance.
• Introduce buffering condition: each sub-task must have sufficient boundary-data buffer.
• Prove a soundness theorem: with adequate buffering, modular decoding preserves fault distance and correctness.
• Develop scheduling for modular sub-tasks to enable concurrent, low-latency decoding.
• Implement edge-vertex decoding and benchmark against offline decoding via Monte Carlo simulations.
• Apply framework to complex logical block networks including 15-to-1 magic-state distillation.

実験結果

リサーチクエスチョン

• RQ1 How can a global decoding problem be decomposed into smaller, parallelizable sub-tasks without sacrificing decoding accuracy?
• RQ2 What buffering width is required so that modular decoding maintains the same fault-tolerance performance as offline decoding?
• RQ3 Can edge-vertex modular decoding achieve low reaction time while preserving fault distance across various fault-tolerant protocols?
• RQ4 Does the buffering condition suffice to guarantee soundness for different lattice-surgery based circuits and distillation protocols?
• RQ5 How does modular decoding perform on large-scale logical-block networks such as 15-to-1 magic-state distillation?

主な発見

• A buffering condition is necessary and sufficient to maintain the same decoding performance as offline decoding when using modular decoding.
• A soundness theorem guarantees decoding with modular decomposition remains effective up to half the fault distance given sufficient buffering.
• Edge-vertex decomposition enables concurrent, low-latency decoding by separating tasks into edge (parallel) and vertex (boundary-dependent) subtasks.
• Scheduling and buffering strategies allow real-time decoding without increasing logical-error rates in large logical-block networks.
• Monte Carlo simulations validate the approach across various buffer sizes and include complex blocks like 15-to-1 magic-state distillation.