[論文レビュー] Reducing End-to-End Latency of Cause-Effect Chains with Shared Cache Analysis

Yixuan Zhu, Yinkang Gao+9 more|arXiv (Cornell University)|Jan 28, 2026

Real-Time Systems Scheduling被引用数 0

ひとこと要約

The paper proposes a time-sensitive, block-level shared cache analysis framework (TSC) that integrates scheduling information to compute tighter WCETs and end-to-end latency for multi-chain cause-effect systems on multicore platforms with shared caches. It reduces end-to-end latency by up to 34% (dual-core) and 26% (quad-core) under certain settings.

ABSTRACT

Cause-effect chains, as a widely used modeling method in real-time embedded systems, are extensively applied in various safety-critical domains. End-to-end latency, as a key real-time attribute of cause-effect chains, is crucial in many applications. But the analysis of end-to-end latency for cause-effect chains on multicore platforms with shared caches still presents an unresolved issue. Traditional methods typically assume that the worst-case execution time (WCET) of each task in the cause-effect chain is known. However, in the absence of scheduling information, these methods often assume that all shared cache accesses result in misses, leading to an overestimation of WCET and, consequently, affecting the accuracy of end-to-end latency. However, effectively integrating scheduling information into the WCET analysis process of the chains may introduce two challenges: first, how to leverage the structural characteristics of the chains to optimize shared cache analysis, and second, how to improve analysis accuracy while avoiding state space explosion. To address these issues, this paper proposes a novel end-to-end latency analysis framework designed for multi-chain systems on multicore platforms with shared caches. This framework extracts scheduling information and structural characteristics of cause-effect chains, constructing fine-grained and scalable inter-core memory access contexts at the basic block level for time-sensitive shared cache analysis. This results in more accurate WCET (TSC-WCET) estimates, which are then used to derive the end-to-end latency. Finally, we conduct experiments on dual-core and quad-core systems with various cache configurations, which show that under certain settings, the average maximum end-to-end latency of cause-effect chains is reduced by up to 34% and 26%.

研究の動機と目的

• Leverage scheduling information and chain structure to improve shared cache analysis for cause-effect chains.
• Provide a scalable, fine-grained inter-core memory access context at the basic-block level.
• Reduce latency pessimism by avoiding over-conservative cache-interference assumptions.
• Develop a safe, integrated framework that yields tighter end-to-end latency estimates for multi-chain systems.

提案手法

• Construct a two-stage analysis framework: architecture-independent scheduling-derived task sequences per core, then architecture-dependent fine-grained shared cache interference analysis.
• Represent basic blocks and loops with relative and interval-based timing to derive absolute execution times relative to system start.
• Compute per-task TSC-WCET using an ILP model that incorporates refined CHMC (cache hit/miss classification) with inter-core context and interference counts.
• Use a hierarchical interference analysis across task instances, loops, and basic blocks, augmented by mutual exclusion information to prune infeasible interferences.
• Merge chains (via back-to-back TT chains or same-period TT chains) to ensure one deterministic job sequence per core, reducing state-space complexity.
• Provide a formal safety proof ensuring that end-to-end latency remains safe under inter-core interference modeling.

実験結果

リサーチクエスチョン

• RQ1 How can scheduling information from cause-effect chains be integrated into shared-cache analysis to reduce WCET pessimism?
• RQ2 How can the structural characteristics of cause-effect chains be exploited to create fine-grained, scalable inter-core memory access contexts?
• RQ3 Can a relative and interval-based timing model at the basic-block level yield tighter CHMC estimates and improved end-to-end latency bounds?
• RQ4 What methods can reduce interference overestimation without sacrificing safety in multicore shared-cache analysis?
• RQ5 What is the impact of the proposed framework on end-to-end latency across dual-core and quad-core setups with varying cache configurations?

主な発見

• Average maximum end-to-end latency is reduced by up to 34% on dual-core systems under certain settings.
• Average maximum end-to-end latency is reduced by up to 26% on quad-core systems under certain settings.