[論文レビュー] Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge

Alessio Carpegna, Alessandro Savino+1 more|arXiv (Cornell University)|Jan 2, 2024

Advanced Memory and Neural Computing被引用数 5

ひとこと要約

Spiker+ は、Python設定可能なフレームワークで、FPGAベースの低電力・低面積の SNN アクセラレータをエッジ推論用に生成します。MNIST と SHD のベンチマークは、競争力のある性能と高いリソース効率を示しています。

ABSTRACT

Including Artificial Neural Networks in embedded systems at the edge allows applications to exploit Artificial Intelligence capabilities directly within devices operating at the network periphery. This paper introduces Spiker+, a comprehensive framework for generating efficient, low-power, and low-area customized Spiking Neural Networks (SNN) accelerators on FPGA for inference at the edge. Spiker+ presents a configurable multi-layer hardware SNN, a library of highly efficient neuron architectures, and a design framework, enabling the development of complex neural network accelerators with few lines of Python code. Spiker+ is tested on two benchmark datasets, the MNIST and the Spiking Heidelberg Digits (SHD). On the MNIST, it demonstrates competitive performance compared to state-of-the-art SNN accelerators. It outperforms them in terms of resource allocation, with a requirement of 7,612 logic cells and 18 Block RAMs (BRAMs), which makes it fit in very small FPGA, and power consumption, draining only 180mW for a complete inference on an input image. The latency is comparable to the ones observed in the state-of-the-art, with 780us/img. To the authors' knowledge, Spiker+ is the first SNN accelerator tested on the SHD. In this case, the accelerator requires 18,268 logic cells and 51 BRAM, with an overall power consumption of 430mW and a latency of 54 us for a complete inference on input data. This underscores the significance of Spiker+ in the hardware-accelerated SNN landscape, making it an excellent solution to deploy configurable and tunable SNN architectures in resource and power-constrained edge applications.

研究の動機と目的

• Enable edge-ready inference of Spiking Neural Networks on FPGAs with low power and small area.
• Provide a fully configurable multi-layer SNN hardware architecture supporting FF-FC and FC-R topologies.
• Develop a Python-based framework to describe networks, train/quantize, and auto-generate VHDL for FPGA deployment.
• Demonstrate competitive MNIST performance and extend to SHD to show framework flexibility.

提案手法

• Introduce a configurable multi-layer SNN architecture with FF-FC and FC-R topologies and various LIF neuron models.
• Develop a library of efficient neuron architectures optimizing area and power, including hard/subtractive reset options and exponential decay handling.
• Provide a Python-based netbuilder to describe networks, integrate with training frameworks (e.g., snntorch), and quantize parameters to fixed-point during deployment.
• Automatically generate VHDL from high-level Python descriptions to create FPGA-ready accelerators with an accompanying testbench.
• Evaluate on MNIST and SHD to compare resource usage, power, and latency against state-of-the-art SNN FPGA accelerators.

実験結果

リサーチクエスチョン

• RQ1 Can Spiker+ generate configurable, low-area, low-power SNN accelerators on FPGAs for edge inference?
• RQ2 How does Spiker+ perform on standard SNN benchmarks (MNIST) versus newer datasets (SHD) in terms of resources, power, and latency?
• RQ3 What architectural and neuron-model choices optimize hardware efficiency while preserving accuracy for edge SNN inference?

主な発見

• On MNIST, Spiker+ は競争力のある精度を、非常に低いリソース使用量（7,612 logic cells and 18 BRAMs）と、画像の全推論で約 180 mW の電力消費で実現します。
• MNIST のレイテンシは 780 μs per image で、最先端の SNN アクセラレータと同等です。
• SHD では、アクセラレータは 18,268 logic cells and 51 BRAMs を使用し、総電力は約 430 mW、完全推論のレイテンシは 54 μs です。
• Spiker+ は SHD で実証された最初の SNN アクセラレータであり、異なる問題に対するフレームワークの柔軟性を強調します。
• フレームワークは Xilinx FPGA ボード用の VHDL モデルを備えたハードウェア生成を可能にし、シミュレーション用のテストベンチを含みます。