이혁재 교수

The effects of shallow trench isolation (STI) on silicon-on-insulator (SOI) devices are investigated for various device sizes with three different gate shapes. Both NMOSFETs and PMOSFETs with the channel region butted to the STI show a reduction in mobility (NMOSFETs and PMOSFETs) and an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI-butted channel region show much less variation in mobility for various channel widths. The degradation

Scale Invariant Feature Transform (SIFT)generates image features widely used to match objectsin different images. Previous work on hardwarebasedSIFT implementation requires excessiveinternal memory and hardware logic [1]. In this paper,a new hardware organization is proposed toimplement SIFT with less memory and hardware costthan the previous work. To this end, a parallelGaussian filter bank is adopted to eliminate thebuffers that store intermediate results becauseparallel operations allow all i

The low-frequency noise characteristics of SOI MOSFETs with shallow trench isolation (STI) structure are investigated for various device sizes with three different gate shapes. Devices with channel region butted to the STI show an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI butted to the channel region show much less increase of noise power spectral density with channel width. From the charge pumping and noise measurement results, t

PURPOSE. This study compared the accuracy of an abutment-framework (A-F) taken with open tray impression technique combining cementon crown abutments, a metal framework and resin cement to closed tray and resin-splinted open tray impression techniques for the 3-implant definitive casts. The effect of angulation on the accuracy of these 3 techniques was also evaluated. MATERIAL AND METHODS. Three definitive casts, each with 3 linearly positioned implant analogs at relative angulations 0, 30, and

In this letter, we propose that f/sub T/ and f/sub max/ properties in partially depleted SOI devices were analyzed in terms of gate electrode layout, body instability, and body resistance of multifinger structure. The speed characteristics were a strong function of the number of fingers and gate types such as T-gate and H-gate structures and were evaluated by g/sub m/ variation (/spl Delta/g/sub m/), extra parasitic capacitance (/spl Delta/C/sub gs/), and ac body instability.

We report a new junction leakage generation phenomenon which was found at specific junction edges on top of which poly-Si gates ran nearby in a 0.35 /spl mu/m design rule actual DRAM chip. As more advanced isolation schemes that enabled less bird's beak were applied, the phenomenon was more evident. After characterizing a set of junction leakage patterns where the relative position of poly gate to the junction edge was systematically varied, a problematic combination of process window and design

We evaluated and analyzed power silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) with gate switching mode during neutron irradiation with our commercial single event effect (SEE) analyzer. Based on evaluation and analysis, we found 1) difference of radiation robustness characteristics; 2) switching mode to be worse condition than non-switching (dc bias condition) mode for 1200-V-rated SiC MOSFETs; and 3) temperature dependence with three manufacturers’ SiC MOSFE

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage o

The authors have investigated the reason for low-noise frequency degradation, frequency dispersion, and harmonic distortion in narrow width SOI MOSFETs with STI. As the channel width decreases, low-frequency noise characteristics, frequency dispersion and harmonic distortion deteriorate due to the larger influence of the interface state which is caused by interface roughness. They have also analyzed the unit circuits performance of VCO, RO, and single MOSFET amplifiers.

Recently, convolutional neural network (CNN)-based object detectors such as You Only Look Once (YOLO) have been intensively studied for applications in robotics, drones, and autonomous driving. Although YOLO can run in real time by using a graphics processing unit, the YOLO hardware implementation has received a great deal of interest due to its power efficiency and the potential for massive chip production. However, extensive memory access and high computation complexity are widely known as bot

A new silicon-on-insulator (SOI) structure for mixed analog-digital applications is proposed where analog and digital MOSFET's are independently optimized. Two types of field oxide are introduced so that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted. From measurements of the body related device characteristics such as the output resistance, the variation of threshold voltage and transconductance, 1/f noise, body res

In this paper we detail the consequences of hot-carrier effects on gate capacitance variation and it's impact on the design margin of each constituent circuit of a 64 Mb DRAM. The degradation mechanism, which produces the capacitance imbalance in specific circuit blocks, is the combination of the increase of gate capacitance in PMOSFET, and the decrease of gate capacitance in NMOSFET. The two dimensional device simulation using MEDICI was also carried out to investigate the gate capacitance vari

In super-resolution, various methods with Convolutional Neural Network(CNN) have recently been proposed. CNN based methods provide much higher image quality than conventional methods. Especially, VDSR outperforms other CNN based methods in terms of image quality. However, it requires a high computational complexity which prevents real-time processing. In this paper, the method to apply a deconvolution layer to VDSR is proposed to reduce computational complexity. Compared to original VDSR, the pr

단일 레이저의 출력 한계를 뛰어넘기 위한 빔결합 방법으로서, 보강간섭 원리를 이용한 타일형 결맞음 빔결합 시스템에 대해 연구하였다. 와트급 출력의 3 채널 결맞음 광섬유 레이저 및 삼각형 배치의 팁-틸트(tip-tilt) 기능을 갖춘 3 채널 출력단을 자체제작 하였다. 모니터링 시스템, 위상제어기, 3 채널 위상변조기 간의 궤환 제어 시스템(closed-loop system)을 구성하고 SPGD 알고리즘을 적용하여, 위상잠금 속도 5~67 kHz, 이상적인 계산값 대비 중심부 광세기 효율 53.3%의 성공적인 3 채널 위상잠금을 구현하였다. 빔결합 소자가 필요 없고, 가장 고출력 가능성을 가진 타일형 결맞음 빔결합을 위한 요소기술 개발이 완료되어, 향후 다채널, 고출력, 고속 제어 연구로 이어질 수 있을 것으로 기대된다.

With video compression standards such as MPEG-4, a transmission error happens in a video-packet basis, rather than in a macroblock basis. In this context, we propose a semantic error prioritization method that determines the size of a video packet based on the importance of its contents. A video packet length is made to be short for an important area such as a facial area in order to reduce the possibility of error accumulation. To facilitate the semantic error prioritization, an efficient hardw