Ik‐Jyae Kim

Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high process

Ferroelectric materials have been intensively investigated for high-performance nonvolatile memory devices in the past decades, owing to their nonvolatile polarization characteristics. Ferroelectric memory devices are expected to exhibit lower power consumption and higher speed than conventional memory devices. However, non-complementary metal-oxide-semiconductor (CMOS) compatibility and degradation due to fatigue of traditional perovskite-based ferroelectric materials have hindered the developm

Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been devel

Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimension

Recently, consumer electronics have moved toward data‐centric applications due to the development of smart electronic devices. Moreover, electronic devices have become highly portable, wearable, and lightweight. These devices require flexible data storage with high density. Furthermore, with the growing demand for larger memory capacity, faster processing speed, and complex data computation, neuromorphic devices have emerged as the next‐generation memory technologies. To meet the needs of next‐g

Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-form

Hafnia-based ferroelectric thin-film transistors (FeTFTs) are regarded as promising candidates for future nonvolatile memory devices owing to their low power consumption, high operational speed, and complementary metal–oxide–semiconductor compatibility. However, the scalability of hafnia-based materials and the feasibility of three-dimensional (3D) device fabrication should be confirmed for ultrahigh-density memory applications. In this work, we demonstrate that FeTFTs can be scaled down to a 10

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To a

The aim of the neuromorphic computing is to emulate energy-efficient and smart data-processing ability of the biological brain, which is achieved by massively interconnected neurons and synapses. The strength of a connection between two neurons is modified by homosynaptic and heterosynaptic plasticity. As current research in the neuromorphic device is mainly focused on emulating homosynaptic plasticity, complex biological functions are not easy to mimic because they require both homosynaptic and

Hafnia-based ferroelectrics have gained much attention because they can be used in highly scaled, advanced complementary metal-oxide semiconductor (CMOS) memory devices. However, thermal stability should be considered when integrating hafnia-based ferroelectric transistors in advanced CMOS devices, as they can be exposed to high-temperature processes. This work proposed that doping of Al in hafnia-based ferroelectric material can lead to high thermal stability. A ferroelectric capacitor based on

Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free

Ferroelectric transistors that use hafnia-based ferroelectric materials are considered as a promising candidate for next-generation memory devices due to their fast operation speed, low power consumption, and high scalability. However, as the polarization switching of ferroelectric materials mostly occurs near the coercive electric field, ferroelectric transistors exhibit non-linear switching characteristics. Thus, precise tuning of voltage pulses is required to achieve multi-level characteristi

Ferroelectric transistors are promising for next-generation display applications due to their nonvolatile memory functionalities, low power consumption, and high-speed operation. However, conventional ferroelectric transistors are fabricated using nontransparent materials with high-temperature processes, making them unsuitable for display applications. In this study, we fabricated a low-thermal-budget transparent ferroelectric transistor at a temperature below 400 °C. This device exhibits a tran

Ferroelectric transistors based on hafnia-based ferroelectrics have emerged as promising candidates for next-generation memory devices. Additionally, hafnia-based ferroelectric transistors are suggested for three-dimensional (3D) memory devices, such as 3D ferroelectric NAND. This paper investigates the utilization of poly-Si as a gate material for hafnia-based ferroelectric transistors in 3D NAND structures. Conventional gate materials, such as TiN or W, are usually deposited in 3D NAND structu

Hafnia-based ferroelectric thin-film transistors (FeTFTs) hold promise for next-generation memory applications like three-dimensional (3D) NAND flash memory, owing to their low power and high-speed operation. However, the utilization of polycrystalline Si (poly-Si) channels imposes limitations on the on-current of the device due to its low mobility. Consequently, alternative channel materials and diverse device engineering methods are being explored. In this study, we fabricated a FeTFT utilizin