[Paper Review] A comparative study of performance of fpga based mel filter bank & bark filter bank

Debalina Ghosh, Depanwita Sarkar Debnath+1 more|arXiv (Cornell University)|Jun 7, 2012

Speech and Audio Processing1 references4 citations

TL;DR

This paper presents an FPGA-based comparative implementation of Mel and Bark filter banks using VHDL on Xilinx Spartan 3E and Virtex-4 devices, employing Bartlett and Hamming windows for FIR filter design. The key finding is that the Bark filter bank achieves superior hardware efficiency, occupying less FPGA resources than the Mel filter bank while maintaining perceptually relevant frequency resolution for speech processing applications.

ABSTRACT

The sensitivity of human ear is dependent on frequency which is nonlinearly resolved across the audio spectrum .Now to improve the recognition performance in a similar non linear approach requires a front -end design, suggested by empirical evidences. A popular alternative to linear prediction based analysis is therefore filter bank analysis since this provides a much more straightforward route to obtain the desired non-linear frequency resolution. MEL filter bank and BARK filter bank are two popular filter bank analysis techniques. This paper presents FPGA based implementation of MEL filter bank and BARK filter bank with different bandwidths and different signal spectrum ranges. The designs have been implemented using VHDL, simulated and verified using Xilinx 11.1.For each filter bank, the basic building block is implemented in Spartan 3E. A comparative study among these two mentioned filter banks is also done in this paper.

Motivation & Objective

• To design and implement efficient, hardware-optimized Mel and Bark filter banks for real-time speech signal processing.
• To evaluate and compare the hardware resource utilization (LUTs, FFs, BRAMs) of Mel and Bark filter banks on FPGA platforms.
• To validate the perceptual relevance of both filter banks by modeling human auditory frequency resolution using psychoacoustic scales.
• To enable integration into a complete speech recognition system by ensuring portability across EDA tools and FPGA technologies.

Proposed method

• Designing 13-band FIR bandpass filters using Bartlett window for the Mel filter bank and Hamming window for the Bark filter bank.
• Implementing the filter banks in VHDL and synthesizing them using Xilinx ISE 11.1 on Spartan 3E and Virtex-4 FPGAs.
• Using Xilinx LogiCORE FIR Compiler to generate optimized FIR filter cores with specified cutoff frequencies and bandwidths.
• Employing ChipScope Pro Integrated Logic Analyzer (ILA) for real-time signal monitoring and validation of internal design behavior.
• Applying frequency warping formulas: Mel(f) = 2595 × log10(1 + f/700) and Bark(f) = 13 × atan(0.76f/1000) + 3.5 × atan(f²/7500²) to define filter center frequencies.
• Validating designs through simulation, synthesis, and hardware testing using a sine wave input and trigger-based waveform capture.

Experimental results

Research questions

• RQ1 How do the hardware resource requirements (LUTs, FFs, BRAMs) of Mel and Bark filter banks compare when implemented on the same FPGA?
• RQ2 What is the impact of window type (Bartlett vs. Hamming) on the frequency response and implementation efficiency of the filter banks?
• RQ3 How does the perceptual frequency resolution of the Mel and Bark scales compare in terms of filter bank design and spectral energy distribution?
• RQ4 To what extent can the filter banks be integrated into a full speech recognition system without exceeding FPGA resource limits?
• RQ5 What are the key differences in design complexity and timing performance between the two filter bank architectures?

Key findings

• The Bark filter bank occupies significantly fewer FPGA resources than the Mel filter bank, as confirmed by device utilization summary comparisons.
• The Mel filter bank design required a 'balanced' synthesis goal due to warnings from the Logicore block instantiation, indicating potential constraints in resource mapping.
• The Bark filter bank demonstrated better hardware efficiency, with lower LUT and flip-flop utilization compared to the Mel filter bank.
• Real-time validation using ChipScope Pro ILA confirmed correct operation, with trigger-based waveform capture showing accurate output responses to input signals.
• The RTL schematics and device utilization reports for both filter banks were successfully generated and analyzed, confirming functional correctness and resource allocation.
• Both filter banks were successfully synthesized and simulated, with results indicating their suitability for integration into a complete speech recognition system.