[Paper Review] Insights into the Mind of a Trojan Designer: The Challenge to Integrate a Trojan into the Bitstream

Maik Ender, Pawel Swierczynski+4 more|arXiv (Cornell University)|Oct 1, 2019

Physical Unclonable Functions (PUFs) and Hardware Security16 references12 citations

TL;DR

This paper presents a novel method for inserting a stealthy hardware Trojan into an FPGA bitstream by manipulating key-based shift-registers in an AES core, enabling the Trojan to bypass self-tests and encrypt data with a fixed, backdoored key. The attack exploits reverse-engineered bitstream analysis and hardware obfuscation via LUTs, demonstrating that partial bitstream exposure is sufficient for effective, undetectable compromise.

ABSTRACT

The threat of inserting hardware Trojans during the design, production, or in-field poses a danger for integrated circuits in real-world applications. A particular critical case of hardware Trojans is the malicious manipulation of third-party FPGA configurations. In addition to attack vectors during the design process, FPGAs can be infiltrated in a non-invasive manner after shipment through alterations of the bitstream. First, we present an improved methodology for bitstream file format reversing. Second, we introduce a novel idea for Trojan insertion.

Motivation & Objective

• To investigate the feasibility of inserting a hardware Trojan into an FPGA bitstream without full design access.
• To improve bitstream reverse engineering techniques for identifying critical hardware components like key registers.
• To demonstrate that partial bitstream exposure can enable effective, stealthy hardware Trojans.
• To explore the implications of such attacks on self-protected cryptographic modules.
• To highlight the need for stronger defense mechanisms against bitstream-level hardware manipulation.

Proposed method

• The authors reverse-engineer the FPGA bitstream using a simplified routing extraction method, focusing on identifying key registers in the AES core.
• They map shift-registers to specific key bit positions by simulating known plaintext/ciphertext pairs and correlating output changes.
• A Trojan is inserted by detaching the key input from flip-flops and replacing it with programmable LUTs that output a fixed key value.
• Each of the 128 key bits is controlled by a dedicated LUT, which is configured to output either 0 or 1 based on the backdoored key.
• The payload is activated via an RS232 interface, allowing the attacker to set the backdoored key during configuration.
• The attack remains undetected during self-tests because only one fixed key is validated, while user data is encrypted with the backdoored key.

Experimental results

Research questions

• RQ1 Can a hardware Trojan be effectively inserted into an FPGA bitstream using only partial bitstream reverse engineering?
• RQ2 To what extent can key-based shift-registers be exploited for creating stealthy backdoors in cryptographic cores?
• RQ3 Is it possible to bypass self-test mechanisms in a hardware-protected AES core through targeted bitstream manipulation?
• RQ4 How effective is bitstream-level obfuscation using LUTs in maintaining stealth and functionality?
• RQ5 What are the practical implications of partial bitstream exposure for hardware security?

Key findings

• The authors successfully reverse-engineered the bitstream to identify key registers responsible for processing AES key bits with high precision using simulation and known plaintext/ciphertext pairs.
• The Trojan was implemented by replacing key input signals to flip-flops with configurable LUTs, enabling full control over the backdoored key.
• The attack remains undetected during self-tests because only a single fixed key is verified, while user data is encrypted with the backdoored key.
• The method requires only partial bitstream access and does not depend on full design knowledge, significantly reducing the attack surface.
• The study demonstrates that bitstream reverse engineering is more feasible than previously assumed, even for complex cryptographic modules.
• The results highlight the vulnerability of self-protected cryptographic cores to targeted bitstream manipulation and call for improved obfuscation and verification techniques.