[Paper Review] Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits

Rajit Karmakar, Santanu Chattopadhyay+1 more|arXiv (Cornell University)|Jan 15, 2018

Physical Unclonable Functions (PUFs) and Hardware Security17 references65 citations

TL;DR

The paper introduces Encrypt Flip-Flop, a MUX-based logic encryption that protects flip-flop outputs to thwart scan-based, SAT, and other attacks with low overhead, validated on ISCAS’89 and ITC’99 benchmarks.

ABSTRACT

Logic Encryption is one of the most popular hardware security techniques which can prevent IP piracy and illegal IC overproduction. It introduces obfuscation by inserting some extra hardware into a design to hide its functionality from unauthorized users. Correct functionality of an encrypted design depends upon the application of correct keys, shared only with the authorized users. In the recent past, extensive efforts have been devoted in extracting the secret key of an encrypted design. At the same time, several countermeasures have also been proposed by the research community to thwart different state-of-the-art attacks on logic encryption. However, most of the proposed countermeasures fail to prevent the powerful SAT attack. Although a few researchers have proposed different solutions to withstand SAT attack, those solutions suffer from several drawbacks such as high design overheads, low output corruptibility, and vulnerability against removal attack. Almost all the known logic encryption strategies are vulnerable to scan based attack. In this paper, we propose a novel encryption technique called Encrypt Flip-Flop, which encrypts the outputs of selected flip-flops by inserting multiplexers (MUX). The proposed strategy can thwart all the known attacks including SAT and scan based attacks. The scheme has low design overhead and implementation complexity. Experimental results on several ISCAS'89 and ITC'99 benchmarks show that our proposed method can produce reasonable output corruption for wrong keys.

Motivation & Objective

• Motivate need for secure logic encryption to prevent IP piracy and overproduction in outsourced IC manufacturing.
• Propose a flip-flop output encryption strategy to curb information leakage through scan chains.
• Achieve protection against multiple attacks (scan-based, SAT-based, path sensitization, logic cone based) with low hardware overhead.
• Provide a practical flip-flop selection procedure to maximize security while minimizing leakage to outputs.

Proposed method

• Insert MUX-based key-gates in front of selected flip-flop outputs to obfuscate Q and/or not-Q paths.
• Select flip-flops for encryption so that every affected output contains all the key-gates (ICOD-based overlap analysis).
• Avoid adding extra hardware beyond MUXes; protection relies on careful placement and traffic of Q/ not-Q signals.
• Treat flip-flop outputs as the unit of encryption to limit information leakage through scan chains.
• Provide an encryption algorithm (Algorithm 2) for selecting flip-flops for secure placement.

Experimental results

Research questions

• RQ1 Can Encrypt Flip-Flop prevent leakage through scan chains and resist common logic-encryption attacks?
• RQ2 How should flip-flops be selected for encryption to maximize security and minimize overhead?
• RQ3 Does the approach impede SAT-based and path-sensitization attacks without extra hardware?
• RQ4 What is the impact on security against widely discussed attacks (logic cone, hill climbing) in practice?

Key findings

• Encrypt Flip-Flop achieves protection by encrypting flip-flop outputs with MUX-based key-gates and careful flip-flop selection.
• The selection strategy ensures that each affected output contains all key-gates, limiting brute-force advantages from logic-cone attacks.
• The scan-based attack context is mitigated since scan chains do not leak key information and controllability/observability is restricted.
• Compared to prior schemes, the method claims low design overhead and resilience against multiple attacks without requiring additional security hardware.
• Experimental results on ISCAS’89 and ITC’99 benchmarks demonstrate the viability of the approach and its security benefits.