[Paper Review] The Challenge of Multi-Operand Adders in CNNs on FPGAs: How not to solve it!

Kamel Abdelouahab, François Berry+1 more|arXiv (Cornell University)|Jun 30, 2018

Advanced Memory and Neural Computing15 references4 citations

TL;DR

This paper investigates two strategies—time-multiplexed serialization and approximate computing using LOA adders—to reduce the high resource cost of multi-operand adders (MOAs) in FPGA-based CNN accelerators. Despite theoretical promise, both approaches fail in practice: serialization incurs excessive logic overhead, and approximate adders provide no area savings due to FPGA logic block architecture, rendering current FPGAs ill-suited for MOA optimization via these methods.

ABSTRACT

Convolutional Neural Networks (CNNs) are computationally intensive algorithms that currently require dedicated hardware to be executed. In the case of FPGA-Based accelerators, we point-out in this work the challenge of Multi-Operand Adders (MOAs) and their high resource utilization in an FPGA implementation of a CNN. To address this challenge, two optimization strategies, that rely on time-multiplexing and approximate computing, are investigated. At first glance, the two strategies looked promising to reduce the footprint of a given architectural mapping, but when synthesized on the device, none of them gave the expected results. Experimental sections analyze the reasons of these unexpected results.

Motivation & Objective

• To address the high resource utilization of multi-operand adders (MOAs) in FPGA-based CNN accelerators, which consume up to 69% of logic resources in some layers.
• To evaluate time-multiplexed serialization as a method to reduce MOA footprint by reusing adder hardware across multiple clock cycles.
• To explore approximate computing using Lower-part OR (LOA) adders to reduce area and power consumption in MOA trees.
• To identify why these optimization strategies fail when synthesized on modern FPGAs, despite strong theoretical expectations.

Proposed method

• Design and synthesize a serializer/accumulator pair for MOAs using VHDL on an Intel Stratix V FPGA, varying cluster sizes to assess logic utilization.
• Implement a binary adder tree as a baseline for resource comparison, using 8-bit operands and Quartus 16.0 synthesis tools.
• Replace exact binary adders in the MOA tree with approximate LOA adders, varying the approximation ratio (0% to 50%) and bit-widths.
• Measure logic utilization in Adaptive Logic Modules (ALMs) and evaluate accuracy using the Mean Relative Error Distance (MRED) metric.
• Compare resource usage and error rates across different approximation ratios and bit-widths to assess trade-offs between accuracy and area efficiency.
• Analyze the impact of FPGA-specific logic blocks (e.g., ALMs with hard-wired full adders) on the effectiveness of approximate adders.

Experimental results

Research questions

• RQ1 Does time-multiplexed serialization of MOAs reduce resource utilization in FPGA-based CNN accelerators?
• RQ2 Can approximate computing using LOA adders significantly reduce the area footprint of MOA trees in FPGAs?
• RQ3 Why do both serialization and approximate computing strategies fail to deliver expected resource savings when implemented on modern FPGAs?
• RQ4 How does the structure of modern FPGA logic blocks (e.g., ALMs with embedded full adders) affect the viability of approximate adders for MOA optimization?
• RQ5 To what extent do the overheads of serializers and the fixed logic block structure nullify the theoretical benefits of MOA optimization techniques?

Key findings

• The serializer/accumulator pair for MOAs consumes more logic elements than a fully pipelined binary adder tree, with serializer overhead growing linearly with the number of operands.
• Approximate LOA adders do not reduce ALM utilization on modern FPGAs, as the logic blocks already contain hard-wired full adders, making OR-gate-based approximation ineffective at the hardware level.
• The Mean Relative Error Distance (MRED) for 8-bit LOA adders remains below 10% even at 50% approximation ratio, indicating acceptable accuracy for some applications.
• Despite low error rates, no area savings are achieved with approximate adders due to the fixed resource cost of FPGA logic blocks, regardless of approximation ratio.
• The high resource cost of MOAs—up to 69% of total logic in the first layer of AlexNet—remains largely unavoidable with current FPGA optimization strategies.
• Current FPGA architectures do not support efficient MOA optimization through serialization or approximation, highlighting the need for specialized DSP blocks for large adders.