Byung‐Wook Min

Single-ended and differential phased array front-ends are developed for Ka-band applications using a 0.12 mum SiGe BiCMOS process. The phase shifters are based on CMOS switched delay networks and have 22.5deg phase resolution and <4deg rms phase error at 35 GHz, and can handle +10 dBm of RF power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) with a 3rd order intermodulation intercept point (IIP3) of +21 dBm. For the single-ended des

This paper presents the design and measurement of a 10-50-GHz low-loss distributed CMOS step attenuator with low phase imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion phase is presented. At 33-37 GHz, the minimum attenuation state loss

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The seri

This letter presents the design and implementation of a Ka-band low noise amplifier (LNA). The LNA is based on a cascode amplifier using 0.12 mum SiGe heterojunction bipolar transistors (HBT). A new design procedure for simultaneous noise and input power matching is developed considering the collector-base feedback capacitance . At 33-34 GHz, the LNA results in a measured gain of 23.5 dB, a return loss of <-20 dB and a noise figure (NF) of 2.9 dB. The input return loss is <-10 dB and the NF is 2

This letter presents the design and implementation of a differential Ka-band variable gain low noise amplifier (VG-LNA) with low insertion phase imbalance. The VG-LNA is based on a 0.12 μm SiGe heterojunction bipolar transistor process, and the gain variation is achieved using bias current steering. The measured VG-LNA gain at 32–34 GHz is 9–20 dB with eight different linear-in-magnitude gain states, and with a noise figure of 3.4–4.3 dB. The measured rms phase imbalance is < 2.5° at 26–40 GHz f

This paper presents a T/R (transmit/receive) module for Ka-band phased arrays using a 0.12 mum SiGe BiCMOS process. The T/R module consists of a low noise amplifier (LNA), power amplifier (PA), 4-bit phase shifter, and single-pole-double-throw (SPDT) switches. The LNA and PA are implemented using SiGe HBTs, and the phase shifter and SPDT switches are based on CMOS switches. The LNA achieves 23.5 dB gain and 2.9 dB noise figure at 34 GHz. The 42% fractional-bandwidth PA has a small-signal gain of

This paper presents a 30-38 GHz 4-bit phase shifter with an integrated LNA using a 0.12 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m SiGe BiCMOS process. The two-stage LNA is implemented using SiGe HBT, and the phase shifter is based on MOSFET switches and miniature low-pass networks. The LNA/phase shifter achieves 1±1.5 dB of gain and 5 dB noise figure at 34 GHz. The RMS phase error is less than 7° at 30-38 GHz. The total chip size is 900×

This paper presents 35 GHz single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression poin

This paper reports on the design and fabrication of a hermetic-compatible wafer-scale package for microwave and millimeter-wave devices. Coplanar waveguide (CPW) lines on a high-resistivity silicon wafer are covered with another silicon wafer using gold-to-gold thermo-compression bonding. Oxide is used as a dielectric inter-layer for CPW feed-throughs underneath the gold sealing ring. A 130-/spl mu/m-high cavity is etched in the cap wafer to remove an impact of capping wafer on CPW lines or RF d

This paper reports on the design and fabrication of wafer-scale packaging for RF MEMS devices. Coplanar waveguide (CPW) lines on a glass wafer are covered with a high resistivity silicon wafer using gold-to-gold thermo-compression bonding. Oxide is used as a dielectric interlayer for CPW feedthrough underneath the gold sealing ring. The designed feedthrough has an insertion loss of 0.06-0.1 dB at 1-50 GHz with a retnrn loss of < -35 dB (per transition). The gold sealing ring is connected tu the

This paper presents a DC-30 GHz single-pole-four-throw (SP4T) CMOS switch using 0.13 mum CMOS process. The CMOS transistor layout is done to minimize the substrate network resistance. The on-chip matching inductors and routing are designed for a very small die area (250times180 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), and modeled using full-wave EM simulations. The SP4T CMOS switch result in an insertion loss of 1.8 dB and 2.7

We demonstrate flexible 3 dB and 6 dB microwave attenuators using multilayer graphene grown by the chemical vapor deposition method. On the basis of the characterized results of multilayer graphene and graphene-Au ohmic contacts, the graphene attenuators are designed and measured. The flexible graphene-based attenuators have 3 dB and 6 dB attenuation with a return loss of less than -15 dB at higher than 5 GHz. The devices have shown durability in a bending cycling test of 100 times. The circuit

A high‐power single‐pole double‐throw transmit/receive (T/R) switch in a silicon‐on‐insulation (SOI) CMOS process is presented. The T/R switch is based on the series–shunt configuration, and the high performance is achieved by utilising SOI characteristics such as floating body transistors and SOI trench (TQ trench). To improve power handling capability, ten thick gate oxide transistors are stacked in transmitter (TX) shunt and receiver (RX) series paths with the source and drain of transistors

This paper reports on the design and fabrication of a wafer-scale package for RF MEMS devices at W-band. Coplanar waveguide (CPW) lines on a high resistivity silicon wafer are covered with another silicon wafer using gold-to-gold thermo-compression bonding. Oxide is used as a dielectric interlayer for CPW feedthroughs underneath the gold sealing ring. A 130 /spl mu/m high cavity is etched in the cap wafer to remove an impact of capping wafer on CPW lines or RF MEMS components. The designed feedt