Chanik Park

In this article, a novel FTL (flash translation layer) architecture is proposed for NAND flash-based applications such as MP3 players, DSCs (digital still cameras) and SSDs (solid-state drives). Although the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, efficient algorithms of an FTL have a significant impact on performance as well as the lifetime. After the dominant parameters that affect the performance and endurance are categor

NAND flash memory based solid-state disk (NSSD) has been used for industrial and military use due to its high reliability and shock resistance. With the bit cost reduction of flash memory and the explosive growth of flash market, NSSD is expected to penetrate into diverse applications such as mobile thin clients, car navigation systems and movie players, which prefer low power consumption, high reliability, high performance and so on. This paper mainly focuses on the development of a high perfor

The ever-increasing requirement for high-performance and huge-capacity memories of emerging embedded applications has led to the widespread adoption of SDRAM and NAND flash memory as main and secondary memories, respectively. In particular, the use of energy consuming memory, SDRAM, has become burdensome in battery-powered embedded systems. Intuitively, though demand paging can be used to mitigate the increasing requirement of main memory size, its applicability should be deliberately elaborated

Journal Article News Media Exposure and Self‐Perceived Knowledge: The Illusion of Knowing Get access Cheong‐Yi Park Cheong‐Yi Park Search for other works by this author on: Oxford Academic Google Scholar International Journal of Public Opinion Research, Volume 13, Issue 4, 1 December 2001, Pages 419–425, https://doi.org/10.1093/ijpor/13.4.419 Published: 01 December 2001

Under the condition that the communication time is relatively shorter than the computation time for a given task, the task duplication-based scheduling (TDS) algorithm proposed by S. Darbha and D.P. Agrawal (1998) generates an optimal schedule. In this paper, we propose an extended TDS algorithm whose optimality condition is less restricted and where the length of the generated schedule is shorter than the original TDS algorithm.

In this paper, we propose a novel, application specific demand paging mechanism for low-end embedded systems with flash memory as secondary storage. These systems are not equipped with virtual memory. A small memory space called an execution buffer is allocated to page an application. An application-specific page manager manages the buffer. The manager is generated by a compiler post-pass and combined with the application image. Our compiler post-pass analyzes the ELF executable image of an appl

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the propo

In this paper, we deal with the data/parity placement problem which is described as follows: how to place data and parity evenly across disks in order to tolerate two disk failures, given the number of disks N and the redundancy rate p which represents the amount of disk spaces to store parity information. To begin with, we transform the data/parity placement problem into the problem of constructing an N/spl times/N matrix such that the matrix will correspond to a solution to the problem. The me

In this paper, we propose a novel FTL (flash translation layer) architecture for NAND flash based applications such as mp3 players, DSCs (Digital still camera) and SSDs (Solid-state disk). Even though the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, its efficient algorithms have a significant impact on performance as well as lifetime. After we categorize dominant parameters that affect performance and endurance, we explore the de

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the propo

With the emergence of the Internet as a significant news medium in the late 1990s, a renewed interest in research on media credibility has developed. Most of the studies made comparisons between TV, newspapers, and online in terms of the public’s credibility in these media (Kim, Weaver, & Willnat, 2000; Flanagin & Metzger, 2000; Johnson & Kaye, 1998; Schweiger, 2000). However, little is known about the—possibly different—determinants of credibility of old and new media, and how credibility of si

Commodity operating systems are considered vulnerable. Therefore, when an application handles security-sensitive data, it is highly recommended to run the application in a trusted execution environment. In response to this demand, hardware-based trusted execution environments such as Intel SGX and ARM TrustZone have been developed in commodity computers. However, hardware-based approaches cannot be quickly upgraded to address design vulnerabilities or to reflect customer feedback. In this paper,

We present an efficient dataflow representation of MPEG-1 Audio (Layer III) Decoder (MP3) algorithm with controlled global states. Although dataflow graph has been a successful representation language for DSP applications, lack of global states makes it unsuitable to some applications that require periodic parameter update and dynamic behavior of function blocks. We show the global states can solve these problems and be fused into dataflow graph without any side effect. With a real-life example

This paper presents an efficient algorithm for network partitioning problem, which improves Fiduccia and Mattheyses' (F-M's) algorithm (1982). We have noticed that the main problem of F-M's algorithm is that the cell move operation is largely influenced by the balancing constraint. In order to handle this kind of inherent limitation in F-M's algorithm, a cost function is adopted which reflects balance degree of a partition as well as its cutset size. The weighting factor R is introduced in the c