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Hong-sik Jung

Ulsan National Institute of Science and Technology · 工学

研究室紹介

Professor Hong-sik Jung's research lab specializes in advanced semiconductor device engineering, with a primary focus on next-generation 3D NAND flash memory technologies. The lab explores innovative materials and device architectures to overcome critical challenges such as low hole mobility in oxide semiconductors and threshold voltage instability in select gate structures. By integrating novel materials like P-type oxide semiconductors and ferroelectric materials with metal gate optimization, the lab develops highly reliable and scalable memory solutions. Their work emphasizes process stability, enhanced charge control, and improved device performance for future high-density data storage applications.

3D NAND flashoxide semiconductorsferroelectric memoryselect gate stabilityhole mobility

Research Overview

Papers
2
Total Citations
4
Papers (5y)
2
Primary Field
工学

Research Output Trend

Figures are computed from collected data and may differ slightly.

Publications per year (5y)
2total
2024
Citations per year (5y)
4total
2024

Selected Papers

2
1
Article|3 citations·2024
An Optimized Device Structure with Improved Erase Operation within the Indium Gallium Zinc Oxide Channel in Three-Dimensional NAND Flash Applications
Seonjun Choi, Jin‐Seong Park, Myounggon Kang, Hong-sik Jung, Yun‐Heub Song
SJR Q2ElectronicsOA

In this paper, we propose an optimized device structure to address issues in 3D NAND flash memory devices, which encounter difficulties when using the hole erase method due to the unfavorable hole characteristics of indium gallium zinc oxide (IGZO). The proposed structure mitigated the erase operation problem caused by the low hole mobility of IGZO by introducing a filler inside the IGZO channel. It facilitated the injection of holes into the IGZO channel through the filler, while the existing P

Electrical and Electronic EngineeringEngineering
2
Article|1 citations·2024
An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications
Seonjun Choi, Myounggon Kang, Hong-sik Jung, Yuri Kim, Yun‐Heub Song
SJR Q2ElectronicsOA

In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably,

Electrical and Electronic EngineeringEngineering

Research Areas

Electrical and Electronic Engineering

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