Jae Ho Lee

This article presents a cryo-CMOS quantum controller IC for superconducting qubits. The proposed globally synchronized clock system internally generates different local oscillator (LO) frequencies using multiple phase-locked loops (PLLs) driven by a common reference clock. It provides flexibility in spectral management as well as scalability for expansion to a large-scale quantum controller. The test chip includes two PLLs, four pulse modulator channels, and two receiver channels. Implemented ch

기업은 경쟁우위를 확보하고 지속적인 성장을 이끌기 위해 기술개발을 위한 R&D 투자 및 혁신활동에 집중해야 한다. 그러나, 기업의 이러한 활동은 언제나 성공하는 것이 아니며, 기술개발의 위험도가 높고 이익의 전용가능성이 낮거나 기업내부의 역량이나 자원이 부족할 경우, 기업의 혁신활동은 저해되기 쉽다. 이러한 상황에서 외부파트너와의 연구협력은 이러한 문제들을 해결할 수 있는 좋은 전략이라고 할 수 있다. 본 연구에서는 한국의 제조업체를 대상으로 각 기업이 기술혁신을 위해 연구협력을 선택할 때 어떤 요인들이 연구협력결정에 영향을 미치는지를 분석하였다. 이를 위해서 과학기술정책연구원(STEPI)에서 수행한 기술혁신조사 데이터를 활용하였으며, 분석결과 기업의 규모가 클수록, 과거의 연구협력경험이 많을수록, 하이테크 기업에 속한 기업일수록 연구협력을 통해 제품혁신을 수행하는 것으로 나타났으며, 혁신실패의 위험성, 자금조달의 어려움, 조직내부의 역량부족, 외부환경요인 등과 같은 혁신활동저해요소

This article analyses the impact of the participation of venture capital (VC) firms on underpricing in 372 Small and Medium-Sized Enterprises (SMEs) brought to Initial Public Offering (IPO) during the period 1999-2001 in KOSDAQ. This period shows a stark contrast in the stock price movements in a way that hot market is abruptly followed by cold market, thus providing a good testing ground for empirical analysis to compare VC impacts in both markets. In this article, it was hypothesised that VC-b

This paper presents a cryo-CMOS dynamic-precision time-interleaved (TI) SAR ADC for FDM-based qubit readout. The ADC includes on-chip background calibration engines to compensate for dynamic inter-channel mismatches of gain, offset, and sampling phases. To mitigate the effect of increased threshold voltage at cryogenic temperature, comparators with native NMOS input stage and sampling switches with low threshold voltage transistors were employed. The implemented IC in 40nm CMOS is verified at 4K

This paper presents a homodyne-demodulation readout IC with continuous-time direct analog integration for superconducting qubits. By integration at the analog frontend, the effective signal-to-noise ratio is efficiently increased, eliminating the need for a high-performance analog-to-digital converter and costly baseband processing for data recovery. The proposed IC, fabricated in 40 nm CMOS, is verified at 4 K in a dilution refrigerator. The readout fidelity, estimated under real-world conditio

This article presents a cryo-CMOS controller that supports derivative removal by adiabatic gate (DRAG) pulses without requiring internal memory. The proposed scheme uses trigonometric relations that substitute a product of two sinusoids by a sum of two frequencies at the same frequencies. It enables embedding the DRAG pulse shaping in an architecture of memory-free real-time direct digital synthesis (DDSs). This work also investigates the effect of inter-channel interference (ICI) and introduces

This article presents a 20-Gb/s/line current-mode (CM) transceiver for dense short-reach on-chip interconnect. The transceiver achieves a systematic crosstalk cancellation (XTC) by balancing the capacitive and inductive coupling. As a receiver frontend, a current-sensing amplifier is designed with an optimum input resistance value for XTC. Without any additional circuits for XTC and equalization, the transceiver implemented in a 40 nm CMOS technology shows a data rate of 20 Gb/s/line and an ener

This paper presents a chopping-less CMOS-based voltage and current reference with a single-transistor noise-suppression loop, where the overall noise is determined by a single transistor while the other noise sources are all suppressed by the gain of the transistor. The reference voltage and current exhibit integrated noises of 2.16μV and 20.3pA with noise floors of 0.45μV and 4.2pA. The chip shows temperature coefficients (TC) of 239.4ppm/°C for the reference voltage (V<sub xmlns:mml="http://ww

A firm seeking to enter a foreign market must make an important strategic decision of which market entry mode to use. Because entry modes involve resource commitments, the initial choice by a firm on a particular entry mode is difficult to change without a considerable loss of time and money. Substantial prior research has been undertaken to explain why firms select a particular entry mode into global markets. However, there exists limited research on this area in the field of foreign apparel br