Jaeha Kim

Additional surgeries for implantable biomedical devices are inevitable to replace discharged batteries, but repeated surgeries can be a risk to patients, causing bleeding, inflammation, and infection. Therefore, developing self‐powered implantable devices is essential to reduce the patient's physical/psychological pain and financial burden. Although wireless communication plays a critical role in implantable biomedical devices that contain the function of data transmitting, it has never been int

Designing softness into robots holds great potential for augmenting robotic compliance in dynamic, unstructured environments. However, despite the body's softness, existing models mostly carry inherent hardness in their driving parts, such as pressure-regulating components and rigid circuit boards. This compliance gap can frequently interfere with the robot motion and makes soft robotic design dependent on rigid assembly of each robot component. We present a skin-like electronic system that enab

Proposes a digital controller for adaptive power-supply regulation that uses sliding control, which is a widely used technique in switching power supplies for its fast transient response and robust stability. A novel reformulation of the sliding control law enables a simple and power-efficient digital implementation. The reference circuit can be either a delay line or a ring oscillator, and the sensor circuits for both cases are discussed. The prototype chip fabricated in 0.25-/spl mu/m CMOS tec

This article addresses issues with designing a blind oversampling clock and data recovery unit (CDR) that meets jitter tolerance specifications. Asymptotic limits on jitter tolerance are derived assuming ideal phase detection based on a priori statistics of the received signal, proving that the coarse timing resolution of blind oversampling CDR relies on a phase detection algorithm that makes good estimates of the signal's statistics with a finite number of discrete samples and at reasonable har

A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and temperature variations. A design methodology of such adaptive-bandwidth PLLs and DLLs is described. To assess the impact of each circuit parameter directly, we derive a discrete-time, open-loop dynamic model of the PLL/DLL that characterizes the change in output variables in response to the sampled error and we e

This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual coupling was found more effective than the conventional T-coil with sizeable driver-side capacitance. An it

This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon th

Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.

This paper describes a noise-based method of estimating the effects of device random mismatch on circuit's transient response, such as delay and frequency. The proposed method models DC mismatch as equivalent AC pseudo-noise and exploits the fast periodic noise analysis (PNOISE) available in RF circuit simulators to compute the resulting variation in the circuit response. While the method relies on Gaussian mismatch distributions and linear perturbation model, it can model and analyze correlatio

This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DCMATCH analysis and offers a large speed-up compared to the traditional Mo

This paper describes an efficient method to characterize the impulse sensitivity function (ISF) of a periodic circuit via periodic AC (PAC) analysis. The paper extends the application of ISF from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. Recognizing that

Leveraging the Boolean intent of digital circuits has enabled a wide set of CAD tools that helped increase the productivity of digital designers. To increase analog designers' productivity requires a similar encapsulation of designer's intent for analog circuits. We argue that linear system models serve this role for almost all analog circuits, while the variables of these models may be in some transformed domains, rather than being the direct voltage/current waveforms of the circuits. We show h

This paper describes a method to perform linear AC analysis on mixed-signal systems which appear strongly nonlinear in the voltage domain but are linear in other variable domains. Common circuits like phase/delay-locked loops and duty-cycle correctors fall into this category, since they are designed to be linear with respect to phases, delays, and duty-cycles of the input and output clocks, respectively. The method uses variable domain translators to change the variables to which the AC perturba

This paper describes an efficient method to characterize the impulse sensitivity function (ISF) of a periodic circuit via periodic AC (PAC) analysis. The paper extends the application of ISF from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. Recognizing that