Ji-Min Kwon
Korea Advanced Institute of Science and Technology · 工学
研究室紹介
Professor Ji-Min Kwon's research lab specializes in next-generation semiconductor technologies, focusing on advanced materials and novel device architectures for ultra-high-speed and energy-efficient electronics. The lab pioneers monolithic 3D integration platforms using III-V semiconductors on glass, atomic layer deposition-grown amorphous oxide semiconductors, and two-dimensional materials like MoS₂ and In₂Se₃ for high-density, low-power memory and logic applications. Key research directions include back-end-of-line (BEOL)-compatible materials growth, 2D semiconductor device physics, and carbon nanotube-based digital circuits with active clock distribution. The lab emphasizes scalable fabrication, statistical device characterization, and integration solutions compatible with existing CMOS processes.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
7The growing demand for sub-THz wireless systems requires not only high-frequency RF devices but also compact, low-loss integration platforms. In this work, we demonstrate a monolithic III-V/glass RF platform using a low-temperature wafer bonding technique, where III-V enables high-frequency transistors and glass offers a low-loss, low-cost, and dimensionally stable platform. The InGaAs HEMTs fabricated on a glass substrate achieve f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink=
Two-dimensional (2D) indium selenide (In2Se3) has great potential for next-generation processing-in-memory applications owing to high intrinsic carrier mobility and strong ferroelectricity. However, the lack of wafer-scale, back-end-of-line (BEOL) compatible growth and inherent polarization-induced hysteresis limit their viability in logic circuits. Here, we report thermal evaporation of a non-ferroelectric κ-phase In2Se3 film that forms uniformly over 4-inch wafer-scale at <450 °C. Structural c
ABSTRACT Monolithic three‐dimensional integration demands embedded memory technologies that achieve extreme density scaling under limited back‐end‐of‐line thermal budget. Atomic layer deposition‐grown amorphous oxide semiconductors (AOS) are attractive for this purpose because of their excellent conformality and intrinsically low off‐state current I OFF, enabling vertical channel transistors (VCTs) for capacitor‐less gain‐cell memory operation. However, in VCT, oxygen‐deficient AOS channels requ
ABSTRACT Atomically thin 2D semiconductors enable excellent electrostatic control even in highly scaled transistors with few‐nanometer gate lengths. The electrical characteristics of 2D transistors can vary significantly with the number of layers, yet how device behavior evolves with channel thickness remains statistically unexplored. This limitation mainly arises from the difficulty of obtaining large numbers of single‐crystal flakes with well‐controlled thickness and fabricating devices. Here,
Single-Flake Transistor In the Research Article (DOI: 10.1002/adfm.202532204), Yongwoo Lee, Haksoon Jung, Jimin Kwon, and co-workers demonstrate that 3-8 layer MoS2 flakes can be reliably classified using pixel intensity contrast in the red, green, and blue optical channels. This approach enables large-scale correlation between optically identified layer number and electrical characteristics, providing a foundation for statistically resolving thickness-dependent electrical behavior in 2D transis
This study presents a benchmark framework for digital blocks featuring an active backside clock distribution network (BSCDN), which incorporates clock buffers and sinks implemented using backside-compatible logic based on carbon nanotube field-effect transistors (CNFETs). The proposed framework includes the fabrication, characterization and TCAD modeling of complementary CNFETs, neural network-based compact modeling, standard cell characterization, and a block-level benchmark comparing the perfo