Jingook Kim

A systematic approach for inductance extraction for via arrays between two parallel planes is presented. Both self and mutual inductance values are obtained based on a cavity model. The physics associated with the via inductances is analyzed, and a rigorous method is developed to derive an equivalent total inductance for multiple via arrays. Analytical equations for the equivalent total inductance are derived in closed forms for simple cases. The proposed method is corroborated with measurements

An electric-field coupling wireless-power-transfer technique is proposed based on the concept of impedance matching. In the proposed electric-field coupling technique, the impedance matching can be easily achieved by controlling the matching inductance. Also, the shielding of the electric field is easy. A metallic plate implemented at the bottom surface of a vehicle is proposed to maximize the coupling capacitance. A simplified experimental setup has been developed, and the maximum power transfe

As layout density increases in highly integrated multilayer printed circuit boards (PCBs), the noise that exists in the power distribution network (PDN) is increasingly coupled to the signal traces, and precise modeling to describe the coupling phenomenon becomes necessary. This paper presents a model to describe noise coupling between the power/ ground planes and signal traces in multilayer systems. An analytical model for the coupling has been successfully derived, and the coupling mechanism w

Power/ground partitioning has been used to supply multivoltage levels and to isolate power/ground noise in high-speed multilayer printed circuit boards. However, the partitioning of the power/ground plane breaks the current return path of the signal current through either the power plane or the ground plane, which causes undesired effects such as signal distortion, crosstalk, and radiation. To control and suppress these undesired effects, we should understand the electromagnetic mechanism associ

An improved definition of target impedance is proposed in this paper, which is derived from the time-domain waveforms of the IC transient current and the allowable voltage fluctuation. The proposed target impedance removes the unnecessary constraint in the original definition and allows for more cost-effective power distribution network (PDN) designs for consumer electronic products. A measurement procedure to obtain IC transient current waveforms is also developed for the PDN designs utilizing

An equivalent circuit model for multilayer power planes with multiple via arrays is proposed. The complexity of the actual geometry is greatly reduced in the circuit model with the accuracy maintained. The model is corroborated by measurements.

Closed-form expressions for transient power distribution network (PDN) noise caused by an IC switching current are derived for a PDN structure comprised of traces with decoupling capacitors. Criteria for identifying a dominant decoupling capacitor for an impulse switching current are also proposed. The derived PDN noise expressions are validated with measurements of currents at both local and bulk capacitors, the PDN impedance, and the total voltage noise in an operating consumer device.

An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of t

The concept of target impedance can be significantly improved, based on the rigorous closed-form expressions for transient supply voltage ripple excited by an integrated circuit (IC) switching current, for the power distribution network (PDN) with power traces that is commonly used in handheld devices. A systematic procedure for developing the target impedance is formulated, which is then applied to the PDN design of a handheld product. From measurements of transient IC switching currents, PDN i

Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages. The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts. In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms

In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.

Partial inductances are computed herein for the via transitions between parallel planes. A hybrid method proposed for the inductance calculation correlates the definition of the partial inductance and a resonant cavity model. The hybrid method is corroborated by comparison with the partial-element equivalent-circuit and the cavity methods, as well as measurements. The portions of the plane net and via net inductances are quantified, and the contribution of each plane current to the plane net ind

A burst stimulus of data is a common activity in circuits and systems. The supply noise voltage waveform induced by a burst train of integrated circuit (IC) switching currents is rigorously derived for a power distribution network (PDN) with power traces, commonly used in handheld devices. Closed-form expressions are proposed to quickly estimate the amount of voltage drop and overshoot and to develop more complete PDN design methodology as improved target impedances. The proposed PDN noise expre

Statistical link analysis methods were previously developed for effective computation of bit error rate due to intersymbol interference (ISI). In addition to ISI, supply voltage fluctuations at output drivers can cause jitter and amplitude uncertainty in I/O links. In this paper, the enhanced statistical link analysis method considering both ISI and supply voltage fluctuations is clearly reformulated and experimentally validated step by step by various measurements. A silicon integrated circuit

An efficient and consistent model for the signal trace with reference discontinuities has been devised. It has been verified that the signal trace model can be used to compute the noise coupling between signal traces and reference planes.