Jiwon Chang

We study the transport properties of deeply scaled monolayer MoS2 n-channel metal-oxide-semiconductor field effect transistors (MOSFETs), using full-band ballistic quantum transport simulations, with an atomistic tight-binding Hamiltonian obtained from density functional theory. Our simulations suggest that monolayer MoS2 MOSFETs can provide near-ideal subthreshold slope, suppression of drain-induced barrier lowering, and gate-induced drain leakage. However, these full-band simulations exhibit l

Neuromorphic computing is of great interest among researchers interested in overcoming the von Neumann computing bottleneck. A synaptic device, one of the key components to realize a neuromorphic system, has a weight that indicates the strength of the connection between two neurons, and updating this weight must have linear and symmetric characteristics. Especially, a transistor-type device has a gate terminal, separating the processes of reading and updating the conductivity, used as a synaptic

Three-dimensional (3-D) topological insulators (TIs) are characterized by the presence of metallic surface states and a bulk band gap. Recently, theoretical and experimental studies have shown an induced gap in the surface state bands of TI thin films. The gap results from interaction of conduction band and valence band surface states from the opposite surfaces of a thin film, and its size is determined by the film thickness. This gap formation could open the possibility of thin-film TI-based me

Achieving a high-quality metal contact on two-dimensional (2D) semiconductors still remains a major challenge due to the strong Fermi level pinning and the absence of an effective doping method. Here, we demonstrate high performance "all-PtSe₂" field-effect transistors (FETs) completely free from those issues, enabled by the vertical integration of a metallic thick PtSe₂ source/drain onto the semiconducting ultrathin PtSe₂ channel. Owing to its inherent thickness

In this paper, we propose a compact model of the short-channel double-gate (DG) JFETs, which are devices intended for low-power logic applications. In order to make the current equation continuous through all operating conditions from the subthreshold to well above the threshold without nonphysical fitting parameters, mobile carriers in depletion regions are considered. For describing the short-channel behavior, relevant parameters extracted from the 2-D analytical solution of Poisson's equation

Using an ab initio density functional theory based electronic structure method with a semilocal density approximation, we study thin-film electronic properties of two topological insulators based on ternary compounds of Tl (thallium) and Bi (bismuth). We consider TlBi${X}_{2}$ ($X=$ Se, Te) and Bi${}_{2}$${X}_{2}Y$ ($X,Y=$ Se,Te) compounds which provide better Dirac cones, compared to the model binary compounds Bi${}_{2}$${X}_{3}$($X=$ Se, Te). With this property in combination with a structural

Recently, a mono-elemental two-dimensional (2-D) material, namely antimonene, with a large band gap, decent mobility and ambient stability has been extensively researched. Interestingly, although antimonene is a semiconductor with a sizable band gap in the monolayer, it is transformed to a metal in the multilayer. Inspired by this thickness dependent semiconductor to metal transition, we propose novel antimonene tunneling field-effect transistors (TFETs) based on the lateral monolayer (semicondu

Abstract The thickness‐modulated phase transition from semi‐metallic (bulk) to semiconductor (a few layers) is the most unique property of pentagonal palladium diselenide (PdSe 2 ). Thus, precise thickness tailoring is essential to fully utilize its unique thickness‐dependent property for exotic device applications. Here, tunable current transport in PdSe 2 based field‐effect transistors (FETs) enabled by layer‐by‐layer thinning of PdSe 2 using mild SF 6 :N 2 plasma is presented. With this top‐d

Metal conversion processes have been instrumental in advancing semiconductor technology by facilitating the growth of thin-film semiconductors, including metal oxides and sulfides. These processes, widely used in the industry, enhance the semiconductor manufacturing efficiency and scalability, offering convenience, large-area fabrication suitability, and high throughput. Furthermore, their application to emerging two-dimensional (2D) semiconductors shows promise in addressing spatial control and

Abstract In this work, the potential of 2D semi‐metallic PtSe 2 as source/drain (S/D) contacts for 2D material field‐effect‐transistors (FETs) through theoretical and experimental investigations, is explored. From the density functional theory (DFT) calculations, semi‐metallic PtSe 2 can inject electrons and holes into MoS 2 and WSe 2 , respectively, indicating the feasibility of PtSe 2 contacts for both n‐ and p‐metal‐oxide‐semiconductor FETs (n‐/p‐MOSFETs). Indeed, experimentally fabricated fl

Two-dimensional (2D) materials have been considered key materials for the future logic devices due to the excellent electrostatic integrity originating from their ultrathin nature. However, the carrier polarity control of 2D material field-effect transistors (FETs) still remains a challenging issue, hindering the realization of complementary logic function in the 2D material platform. Here, we report a comprehensive study on the electrical characteristics of PdSe₂ FETs with different

Achieving effective polarity control of n- and p-type transistors based on two-dimensional (2D) materials is a critical challenge in the process of integrating transition metal dichalcogenides (TMDC) into complementary metal-oxide semiconductor (CMOS) logic circuits. Herein, we utilized a proficient and nondestructive method of electron-charge transfer to achieve a complete carrier polarity conversion from p-to n-type by depositing a thin layer of aluminum oxide (Al 2 O 3 ) onto tungsten diselen

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS 2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS 2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlO x /Al 2 O 3 and a double-gate structure employing high- k dielectric HfO 2 . Due to the superior

Low contact resistance can be achieved in the metallic and semiconducting PtSe₂ lateral heterostructure through the thickness-dependent phase transition in PtSe₂.