Jongho Ahn
Seoul National University · 情報科学
研究室紹介
Professor Jongho Ahn's research lab focuses on computer architecture and systems, with a strong emphasis on designing energy-efficient, scalable, and high-performance computing systems for emerging manycore and exascale platforms. The lab explores innovative interconnect topologies such as HyperX, adaptive routing algorithms, and novel memory system architectures—including multicore DIMMs and hierarchical register files—to address bandwidth, power, and scalability challenges. Research also extends to stream processing, microarchitecture simulation, and the impact of process technology scaling on reliability and energy efficiency. The lab integrates hardware-software co-design principles to optimize system-level performance and energy efficiency.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
15In the push to achieve exascale performance, systems will grow to over 100,000 sockets, as growing cores-per-socket and improved single-core performance provide only part of the speedup needed. These systems will need affordable interconnect structures that scale to this level. To meet the need, we consider an extension of the hypercube and flattened butterfly topologies, the HyperX, and give an adaptive routing algorithm, DAL. HyperX takes advantage of high-radix switch components that integrat
This paper describes an experimental evaluation of theprototype Imagine stream processor. Imagine [Imagine: Media processing with streams] is a stream processor that employs a two-level register hierarchy with9.7 Kbytes of local register file capacity and 128 Kbytesof stream register file (SRF) capacity to capture producer-consumerlocality in stream applications. Parallelism is exploitedusing an array of 48 floating-point arithmetic unitsorganized as eight SIMD clusters with a 6-wide VLIW perclu
With their significant performance and energy advantages, emerging manycore processors have also brought new challenges to the architecture research community. Manycore processors are highly integrated complex system-on-chips with complicated core and uncore subsystems. The core subsystems can consist of a large number of traditional and asymmetric cores. The uncore subsystems have also become unprecedentedly powerful and complex with deeper cache hierarchies, advanced on-chip interconnects, and
Abstract Transmission and analytical electron microscopy have been used to study the diagenesis of the trioctahedral component of phyllosilicates (principally chlorite) in argillaceous core samples (depths of 1750, 2450, and 5500 m) from the Gulf Coast. Chlorite was observed as 100-150-Å thick packets intergrown within mixed-layer illite/smectite in the 2450-m sample and was more abundant and larger in packet thickness in the 5500-m sample. The chlorite is disordered in stacking sequence as char
Continuous evolution in process technology brings energy-efficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, there are proposals aiming at better main-memory energy efficiency by dividing a memory rank into subsets.
Demand for memory capacity and bandwidth keeps increasing rapidly in modern computer systems, and memory power consumption is becoming a considerable portion of the system power budget. However, the current DDR DIMM standard is not well suited to effectively serve CMP memory requests from both a power and performance perspective. We propose a new memory module called a multicore DIMM, where DRAM chips are grouped into multiple virtual memory devices, each of which has its own data path and recei
Exceptionally small spheres (nanospheres) of hematite (diameters between 120 and 200 nanometers) occur in the Marra Mamba Iron Formation of the Hamersley Basin, Australia. The nanospheres are clustered into small aggregates and may have formed by structural ordering and dehydration of colloidal iron hydroxide particles. Individual spheres consist of numerous thin, curved hematite platelets surrounding a central void that is approximately half the diamter of the sphere; this texture suggests that
Abstract Alternating mica-like and smectite-like layers of rectorite give rise to periodically varying contrast in 10-Å lattice fringes, yielding a periodicity of 20 Å in a transmission electron microscopic study. Expansion of rectorite using dodecylamine hydrochloride yields a three-layer repeat of thickness 32–35 Å, consisting of a basic 20-Å unit, identical to that in images of collapsed, dehydrated rectorite, and a 12-15-Å thick, intercalated organic layer. Thin packets of layers derived by
Abstract Transmission electron microscope (TEM) images of mixed-layer illite/smectite (I/S) from Gulf Coast shales obtained earlier by the authors have been reexamined by comparing them with the calculated images of G. D. Guthrie and D. R. Veblen. Ordered two-layer periodicity was not detected in the 1750- and 2450-m depth samples, for which X-ray powder diffraction (XRD) showed 20% and 40% illite randomly interstratified in I/S, respectively. Two-layer periodicities that occur in images of the
Many important applications exhibit large amounts of data parallelism, and modern computer systems are designed to take advantage of it. While much of the computation in the multimedia and scientific application domains is data parallel, certain operations require costly serialization that increase the run time. Examples include superposition type updates in scientific computing and histogram computations in media processing. We introduce scatter-add, which is the data-parallel form of the well-
Data-parallel memory systems must maintain a large number of outstanding memory references to fully use increasing DRAM bandwidth in the presence of rising latencies. Additionally, throughput is increasingly sensitive to the reference patterns due to the rising latency of issuing DRAM commands, switching between reads and writes, and precharging/activating internal DRAM banks. We study the design space of data-parallel memory systems in light of these trends of increasing concurrency, latency, a