Jun-Eun Park

This paper describes a capacitive touch-screen panel (TSP) readout IC that provides a reconfigurable SNR and frame rate with high noise immunity and touch sensitivity. The readout IC mitigates severe noise interference with a lock-in sensing architecture. In addition, a band-pass filtering effect by the TSP and charge amplifier further improves the noise immunity. A differential sensing scheme is employed to enhance the touch sensitivity and to reject a common-mode noise. A column-parallel incre

This paper presents a fully synthesizable successive-approximation-register (SAR) analog-to-digital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and d

This paper presents a touch sensing analog front end (AFE) for capacitive touch-screen integrated into an ultra-thin display. Reduced distance between the touch screen and display causes large capacitive coupling, resulting in increased parasitic capacitance and reduced touch sensitivity. Display noise interference is worse due to the large coupling capacitance. Hence, it is a challenge to design an AFE capable of accurate and energy efficient sensing of a touch input in the integrated touch-scr

Individual power management is required to adjust the supply voltage of intellectual properties (IPs) for better energy efficiency in a system-on-chip design [1]. For this application, integrated digital low-dropout regulators (DLDOs) are attractive with better scalability, smaller sizes of pass gates, and wider input ranges. Recently, new DLDO architectures have been presented that remove an output-decoupling capacitor [1], [2] and regulate large load currents [3], [5] while offering high curre

This paper describes the design of an analog front-end (AFE) for capacitive touch-screen controllers that provide highly enhanced noise immunity. The proposed AFE mitigates severe noise interference using a multi-channel-driving (MCD) TX scheme and a noise-filtering RX structure. The MCD scheme with a frequency hopping technique modulates mutual capacitances in a touch-screen panel (TSP) using low-offset orthogonal sequences, spreading the noise interference. In the RX sensing block, a pre-filte

This letter presents an event-driven digital low-dropout regulator (DLDO) with an adaptive linear/binary two-step search achieving a fast transient response. A two-dimensional (2-D) circular shifting register (CSR) offers an adaptive linear-search regulation. When a large voltage droop occurs, the CSR activates a fast-tracking mode that provides immediate recovery from the droop. Once the linear search by the CSR is completed, a subrange successive-approximation register (Sub-SAR) conducts the b

This brief presents a two-step hybrid integrator (TSHI) that can operate at a wide supply voltage range, which is demonstrated with a third-order ΔΣ analog-to-digital converter (ADC). The proposed TSHI consists of a zero-crossing-detector (ZCD)-based integrator and an inverter-based integrator. In the coarse-integration step, the ZCD-based integrator performs a fast integration without concern for overshoot or detection delay issues. In the fine-integration step, the inverter-based integrator pe

We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10(-12) bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of -11 dBm, -8 dBm, and -2 dBm for data rates o

This paper presents a noise-shaping SAR ADC for IoT sensor applications. The ADC exploits a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order passive noise-shaping loop without a quiescent current. To reduce harmonic distortion induced by mismatches between MSBs, thermometer-coded 3-bit MSBs are implemented with a simple shift register-based dynamic element matching (DEM) technique. Furthermore, a programmable majority-voting (PMV) t

This article presents a synthesizable digital low-dropout regulator (DLDO) that precludes the use of an output load capacitor. For efficient regulation, the DLDO consists of fine and coarse loops that have different load conditions to operate. The dual loops are made of typical standard cells to improve the synthesizability. In the coarse loop, a comparator (CMP)-triggered oscillator is employed to generate a high-frequency clock signal without concerning the metastability in the CMP. In order t

Touch screens have recently been adopted not only for smartphones but also for tablet PCs and home appliances that have touch-screen panels (TSPs) larger than 10 inches. However, there are many sources of noise that affect touch detection, and some of these noise sources, such as charger noise, significantly affect the capacitance variation needed to detect touch input and lead to inaccurate touch detection [1–2]. For example, as shown in Fig. 11.6.1, common-mode supply noise results in large pe

Digital low-dropout regulators (DLDOs) are commonly used in low-power system-on-chips (SoCs) because of their low-voltage operation and fast transient response via the digital control of a power gate. However, the digital control of the power gate results in an output voltage ripple and a decrease in the power-supply rejection (PSR). In addition, the transient performance of DLDOs depends strongly on the operating clock frequency. Several techniques such as event-driven operation [1], VCO-embedd

This article proposes a fully integrated hybrid low-dropout regulator (HLDO) that features an ultralow dropout and a highly improved transient response. This HLDO incorporates a residue-current-locked loop (RLL) that realizes joint regulation using a residue-compensating analog LDO (RLDO) and residue-triggered asynchronous digital LDO (DLDO). The RLDO supplements the residual current to compensate for the current quantization error (CQE) of the DLDO, thus eliminating the limit cycle oscillation

This brief presents a 32 Gb/s driver for a Mach-Zehnder modulator (MZM) and an electro-absorption modulator (EAM). A push-pull current-mode logic driver is chosen to achieve a better power efficiency and a large voltage swing. A double cascode with thin oxide transistors is employed to mitigate the over-voltage stress associated with a large output voltage swing. At the same time, shunt-peaking inductors are incorporated in a compact way to extend the bandwidth and to have a flat group delay. Th

This brief presents a highly synthesizable digital low-dropout regulator (DLDO) based on adaptive clocking and an incremental regulation scheme. With these features, the clock frequency of the shift registers is adaptively changed according to load voltage, and most of the voltage droop is stably recovered in one clock transition using voltage-unit-resolution pass gates. Moreover, the DLDO is fully synthesized using an auto place-and-route (P&R) process except pass gates and an on-chip metal-oxi