Kee-Won Kwon
Sungkyunkwan University · 工学
研究室紹介
Professor Kee-Won Kwon's research lab specializes in advanced materials and device physics for microelectronics and thin-film transistor technologies. Key research directions include the development of high-performance amorphous oxide semiconductors—particularly a-GIZO (amorphous gallium-indium-zinc oxide)—for transparent and flexible electronics, with a focus on optimizing electrical properties, interface engineering, and reliability. The lab also investigates metallization challenges in integrated circuits, such as electromigration in Cu interconnects and interfacial reactions in barrier layers like Ta and Ta₂O₅, aiming to enhance device performance and thermal stability. Their work bridges fundamental materials science with practical applications in next-generation semiconductor devices.
Research Overview
Research Output Trend
Figures are computed from collected data and may differ slightly.
Selected Papers
15The effects of texture and grain structure on the electromigration lifetime of Cu interconnects are reported. Using different seed layers, [111]- and [200]-textured CVD Cu films with similar grain size distributions are obtained. The electromigration lifetime of [111] CVD Cu is about four times longer than that of [200] CVD Cu. For Damascene CVD Cu interconnects, the electromigration lifetime degrades for linewidths in the deep submicron range because the grains are confined as a result of confo
Amorphous-gallium-indium-zinc-oxide (a-GIZO) thin filmtransistors (TFTs) are fabricated without annealing, using processes and equipment for conventional a-Si:H TFTs. It has been very difficult to obtain sound TFT characteristics, because the a-GIZO active layer becomes conductive after dry etching the Mo source/drain electrode and depositing the a-SiO2 passivation layer. To prevent such damages, N2O plasma is applied to the back surface of the a-GIZO channel layer before a-SiO2 deposition. N2O
We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had a field effect mobility of 5 cm2/V s, a threshold voltage of 0.2 V, and a subthreshold swing of 0.2 V/decade. Ar plasma was treated on the source/drain region of the a-GIZO active layer to reduce the series resistance. After Ar plasma treatment, the surface of the source/drain region was divided into In-rich and In-deficient regions. The a-GIZO TFT also had a constant sheet
This letter describes the formation of a thin amorphous layer at the tetragonal-Ta/Cu interfaces, which appear in copper metallization structures of microelectronic devices. The disordered layer grows up to 4 nm when annealed at between 400 and 600 °C. Since Ta and Cu are immiscible according to thermodynamic data, this is an unusual observation. A mechanism for the amorphous phase formation is proposed using both physical and chemical considerations. A high content of Cu is detected in the Ta l
The thermal degradation of the Ta/sub 2/ O/sub 5/ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta/sub 2/O/sub 5/ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850/spl deg/C. The Ta/sub 2/O/sub 5/ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current c
Crystallographic orientations between thin-sputtered Cu film and β-Ta adhesion layer have been studied using high resolution electron microscopy and electron diffraction. Tetragonal β-Ta deposited on SiO2 has a strong texture with its closest packed plane (002) parallel to the film surface. On (002) β-Ta, the growth of (111) Cu is preferred. Even though more than 100 β-Ta grains are found under a single Cu grain, the Ta grains under a Cu grain have long range in-plane texture with [330] directio
The thermal degradation of the Ta205 capacitor during BPSG reflow has been studied. The cause of deterioration of TazO5 with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta205 capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained.
A thermally robust Ta/sub 2/O/sub 5/ capacitor applicable to the 1 Gbit DRAM and beyond was developed. From the degradation-free Ta/sub 2/O/sub 5/ capacitor with a TiN/poly-Si top electrode, the sputtered-TiN was replaced by the PECVD-WN to improve the step coverage for the complicated capacitor structure. The Ta/sub 2/O/sub 5/ capacitor with a PECVD-WN/poly-Si top electrode had a better thermal stability in the complicated capacitor structure than that with sputtered-TiN/poly-Si, as a result. C
한국학술진흥재단의 연구분야분류표에 의하면 지적학은 지역개발의 중분류아래 소분류항목으로 배정되어 있어 독립된 학문분야로 인정받지 못하고 있다. 따라서 이 연구의 목적은 현행 지적학 학문분류체계의 문제점을 찾아내고 개선방안을 제시하는데 있다. 이를 위해 지적학의 학문적 정의와 연구대상, 지적학 관련의 학문적 성과, 지적학 교육제도와 교과목의 현황과 특징을 분석하였으며, 학문분류체계와 문헌분류에서의 분류현황을 살펴보았다. 그 결과 지적학을 복합학의 대분류영역에 배정하여 중분류로 상향 이동시키고 소분류와 세분류 항목을 설정하여 지적학의 학문분류체계를 개선할 수 있는 것으로 나타났다.
The thermal degradation of the Ta/sub 2/O/sub 5/ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta/sub 2/O/sub 5/ with the TiN top electrode was found to be the oxidation of TiN. By inserting poly-Si between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850/spl deg/C. The Ta/sub 2/O/sub 5/ capacitor with the TiN/poly-Si top electrode was integrated into 64 Mbit DRAMs and excellent leakage current characteristic
In this paper, we provide a thorough analysis and enhancement techniques of the linearity between the input voltage and output current in charge storage field effect transistor (FET) cells for a vector–matrix multiplier array in neural networks. A planar floating gate FET cell revealed superior linearity, because of boosting the floating gate using a drain voltage through capacitive coupling. If the coupling capacitance is extended by up to half of the gate capacitance, the coefficient of determ
Abstract In the copper metallization adopted for better speed and reliability in microelectronic devices, the choice of underlayer is one of the major concerns. Its requirements include low electrical resistance, adhesion to Cu and adjacent dielectric materials, confinement of Cu from drifting, and nucleation and texture enhancement of the overlying Cu film. Metallic tantalum is a very promising candidate. In this paper, the thermal stability of Cu/Ta interfaces is investigated to estimate the r