Ki-Seok Jeong

A simple and compact microstrip-fed ultrawide-band (UWB) printed monopole antenna with band-notch filter is proposed. The antenna is composed of two monopoles of the same size and a small strip bar which leads to the desired high attenuation at the notch frequency. The band-notch mechanism and current distribution of the antenna are examined. Finally, the frequency-domain characteristics, such as system transfer function and group delay, of the proposed identical monopole antenna pair are analys

A novel compact and wideband coplanar waveguide(CPW)-fed monopole antenna is proposed. To increase the impedance bandwidth, two parasitic elements and three slots are added, which structures are optimised by a parametric analysis. The antenna operates over 3.1 to 11 GHz for the return loss of less than −10 dB. Radiation patterns also show very well omnidirectional performance of the proposed antenna.

A novel two-channel multiple input multiple output (MIMO) antenna for handset terminals is proposed. The antenna is basically composed of two folded monopoles and is designed to operate in WiBro (Wireless Broadband Internet; the Korean version of mobile WiMax) service band, 2.30–2.39 GHz. To decrease mutual coupling between the antennas, ground wall and connecting line are added. Good impedance matching and enhanced isolation performances are observed. Radiation patterns clearly show omnidirecti

Digital mobile communication technologies, such as next generation mobile communication and mobile TV, are rapidly advancing. Hardware designs to provide baseband processing of new protocol standards are being actively attempted, because of concurrently emerging multiple standards and diverse needs on device functions, hardware-only implementation may have reached a limit. To overcome this challenge, digital communication system designs are adopting software solutions that use central processing

Abstract DiPS (Diversified Plasma Simulator), a new versatile linear machine (length=3400 mm, diameter=200‐600 mm), is developed for the simulations of divertor, space and processing plasmas with various electric probes: fast‐scanning systems with single, triple, and Mach Probes, slow‐scanning water‐cooled single probe, griddedenergy analyzer (GEA), and several fixed single probes. For the verification of current probe theories and the development of new theories with magnetic vector field, coll

Owing to advancement in 4 G mobile communication and mobile TV, the throughput requirement in digital communication has been increasing rapidly. Thus, the need for efficient error-correcting codes is increasing. Furthermore, since most mobile devices operate with limited battery power, low-power communication techniques are attracting considerable attention lately. In this article, we propose a novel low-power, low-density parity check (LDPC) decoder. The LDPC code is one of the most common erro

We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulati

In this pap er, we present sever al optimization techniques for power reduction utilizing circuit symmetries. There are four kinds of symmetries that we dete ct in a given circuit implementation. First, we pr op ose an algorithm for dete cting the four different typ es ofsymmetries in a given circuit implementation of a Boole an function. Sever alre-synthesis techniques utilizing such symmetries are prop ose d. These techniques enable us to optimize power consumption and delay with no (or very l

Convolutional neural networks (CNNs) have demonstrated promising results in various applications such as computer vision, speech recognition, and natural language processing. One of the key computations in many CNN applications is matrix multiplication, which accounts for a significant portion of computation. Therefore, hardware accelerators to effectively speed up the computation of matrix multiplication have been proposed, and several studies have attempted to design hardware accelerators to p

A new probe set, called the Gundestrup-emissive-triple (GET) probe, is developed to measure the rotational velocity, plasma potential, electron temperature, and plasma density profiles simultaneously in Hanbit mirror device. The GET probe system is composed of the Gunderstrup, an emissive, and a triple probe installed in one boron nitride probe holder, which is attached on the fast scanning injection system. Rotational and parallel flow velocities are deduced from the measurement of Gundestrup p

Abstract Although theory of the triple probe for Maxwellian plasma is well known, analysis with ion beams has not been established. Since plasma parameters, especially electron temperature, are distorted severely in the presence of supersonic ion beams, a new model for deducing electron temperature is introduced by solving the governing equations of the triple probe including the beam currents to three probe tips through simple assumptions. (© 2006 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a g

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. Recently, a new model of glitch analysis, called G-vector has been proposed. The power of the model is that, unlike the existing ones which model only the propagation of glitches to count the number of glitches in the circuits, it allows one to model the generation, propa

In this paper, we present several optimization techniques for power reduction utilizing circuit symmetries. There are four kinds of symmetries that we detect in a given circuit implementation. First, we propose an algorithm for detecting the four different types of symmetries in a given circuit implementation of a Boolean function. Several re-synthesis techniques utilizing such symmetries are proposed. These techniques enable us to optimize power consumption and delay with no (or very little) ar