Sanghun Kwon

This paper presents a flaw in the permission scheme of Android. The Android framework enforces a permission-based security policy where an application can access the other parts of the system only when the application is explicitly permitted. The security of the framework depends to a large extent on the owner of a device since the authorization decisions are mainly made by the user. As a result, the permission scheme imposes much of the administrative burden on the user instead of keeping it si

The far-reaching work of Dahmani–Guirardel–Osin (2017) and recent work of Clay– Mangahas–Margalit (2021) provide geometric approaches to the study of the normal closure of a subgroup (or a collection of subgroups) in an ambient group G . Their work gives conditions under which the normal closure in G is a free product. In this paper we unify their results and simplify and significantly shorten the proof of the theorem of Dahmani–Guirardel–Osin (2017).

Satisfying the timing constraint is the utmost concern in the integrated circuit design and it is true that most critical timing paths in a circuit cover one or more arithmetic components such as adder, subtractor, and multiplier of which addition logic is commonly involved. This work addresses the problem of redesigning the addition logic (in a form of hybrid adder) on a critical timing path to meet the timing constraint while minimally allocating the required addition logic. Unlike the convent

Balsa developed by Advanced Processor Technology (APT) Group of Manchester University presents robust design environment that supports both a framework for synthesizing asynchronous hardware systems and the language for describing such systems. In this paper, a design of microprocessor, MSP430, in balsa language and the functional verification of the controller is presented. Back-end retargeting is performed as a part of the design methodology in balsa. By back-end retargeting procedure, a new t

Despite the rapid growth of green vehicle markets in recent years, its components including control units are still very expensive compared to those on the gasoline/diesel powered vehicle. In order to reduce costs and save more space on the vehicle, integration technology is required to develop. This paper proposes the development progress and optimization of integrated Power Control Unit of Hybrid/Electric vehicle.

The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained tradeoffs in the power-delay tradeoff curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and precisions. Thus the method allows us to expand the original design space of a specific type of adder into the more f

We prove that the full automorphism group and the outer automorphism group of the free group of countably infinite rank are coarsely bounded. That is, these groups admit no continuous actions on a metric space with unbounded orbits, and have the quasi-isometry type of a point.

In this paper, we propose a high performance asynchronous on-chip bus with multiple issue and in-order/out-of-order completion for a Globally Asynchronous Locally Synchronous (GALS) design. The proposed bus implementation can be characterized with distributed and modularized control units based on a layered architecture to support multiple issue and in-order/out-of-order completion. Simulation results reveal that throughputs of asynchronous on-chip buses with multiple issue and in-order/out-of-o

We show that an Anosov map has a geodesic axis on the curve graph of a torus. The direct corollary of our result is the stable translation length of an Anosov map on the curve graph is always a positive integer. As the proof is constructive, we also provide an algorithm to calculate the exact translation length for any given Anosov map. The application of our result is threefold: (a) to determine which word realizes the minimal translation length on the curve graph within a specific class of wor

The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more