김봉진 교수

ABSTRACT Manuscript Type: Conceptual Research Question/Issue: Board reforms around the globe, corporate governance failures, and equivocal research findings provide the impetus for studying boards from a perspective different from the current emphasis on control and service roles. A board's strategic role is conceptualized and the impact of board diversity and leadership structure on the speed and breadth of top management team (TMT) strategic capabilities is explicated. Research Findings/Insigh

Government regulation in an industry is an intermediary in the principal-agent relationship that acts as a substitute for internal governance mechanisms. We propose a model for studying how different forms of deregulation (frame-breaking, metamorphic, piecemeal, and plodding) impact variations in the speed of adaptation of internal governance mechanisms to the theoretical predictions of agency theory and resulting performance implications. We develop illustrative propositions for a set of contin

An 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) is demonstrated in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16x TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm <sup xmlns:mml="http://www.w3.

The effects on electrical properties of solution-processed indium zinc tin oxide (IZTO) thin film transistors (TFTs) by nitrogen incorporation were investigated as a function of annealing temperature. The nitrogen incorporation was controlled by NH(4)OH addition into a precursor solution of zinc, indium, and tin chlorides. At 600 degrees C annealing, the nitrogen-doped IZTO TFTs showed a field-effect mobility of 5.33 cm(2)/V s with an on/off ratio of 2.05 X 10(7). By the nitrogen incorporation,

A fully-digital VCO-based ADC featuring a novel beat frequency detection scheme is demonstrated in 65nm LP CMOS. The proposed beat frequency based ADC is unique compared to previous VCO-based ADCs in that it is highly effective in measuring extremely small changes (e.g., 0.01%) in the VCO frequency within a short sampling time (e.g., 100 VCO periods). Direct amplifier-less A-to-D conversion of a 1.6mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">

An adaptive PLL that maximizes the timing compensation between clock and data, commonly referred to as the clock data compensation effect, is demonstrated in 32 nm SOI. A number of previous adaptive PLL designs have successfully proven that processor operating speed can be improved by modulating the clock path delay or the PLL output clock period using the resonant supply noise. In this work, we take the adaptive PLL concept one step further by achieving optimal clock data compensation across a

A VCO-based ADC featuring a multi-phase beat frequency based quantization scheme with first order noise shaping is demonstrated in a 65nm CMOS process. The proposed ADC is unique in that it can achieve high resolution (e.g. 6–7 ENOB) for signals with extremely small amplitudes (e.g. <1mV). This allows us to remove or simplify the pre-conditioning amplifiers, reducing power consumption as well as the overall system complexity. The proposed ADC achieves 43dB SNDR for a 1mV input signal while achie

In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a

In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the IEEE 802.16e WiMAX standard. The decoder supports all the code rates and codeword lengths defined in the standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. In addition, the decoder adopts a novel scheduling scheme named s

Von Neumann architecture is recently facing a critical challenge with the high demands of energy-efficient computing hardware for a variety of machine learning tasks such as image classification. In particular, battery-operated mobile devices with limited power budget cannot process artificial neural networks (ANNs) with relatively low complexity by using traditional digital circuits and architectures. The key challenge with the traditional Von Neumann architecture is its energy-inefficient data

In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the WiMAX 802.16e standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors. Furthermore, the decoder adopts a novel scheduling scheme, named as stride scheduling, to remove the conventional flexible permutation network and also mini