최병덕 교수

The zero-potential scanning circuit is widely used as read-out circuit for resistive sensor arrays because it removes a well known problem: crosstalk current. The zero-potential scanning circuit can be divided into two groups based on type of row drivers. One type is a row driver using digital buffers. It can be easily implemented because of its simple structure, but we found that it can cause a large read-out error which originates from on-resistance of the digital buffers used in the row drive

We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nod

The development of microelectromechanical system (MEMS) processes enables the integration of capacitive sensors into silicon integrated circuits. These sensors have been gaining considerable attention as a solution for mobile and internet of things (IoT) devices because of their low power consumption. In this study, we introduce the operating principle of representative capacitive sensors and discuss the major technical challenges, solutions, and future tasks for a capacitive readout system. The

The design and experimental results of a 192-bit low-cost and high-current-driving PDP data driver IC implemented in a 100 V silicon-on-insulator (SOI) lateral double-diffused MOS (LDMOS) process are presented. The LDMOSFET is the device of a choice in this design, because it is compatible with low-voltage transistors for logic circuits. To maximize the current driving capability and protect the pull-up n-channel LDMOSFET of the output buffet, zener diode circuits are established between the gat

The panel AC power, the largest portion of power consumption of data driver circuits in TFT-LCDs, comes from charging and discharging quite large capacitive loads, data lines. The proposed stepwise data driving method can reduce the panel AC power consumption into only a few percent of that of conventional ones if the number of step is large enough. In the proposed driving method, external capacitors supply charge to loads in stepwise manner, and the charge returns to the capacitors instead of b

An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post‐processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate

Insufficient pixel charging time has come up as one of the most serious problems, as the resolution format of TFT-LCDs grows higher and the display area gets larger. In order to resolve the problem, we have proposed a new driving scheme coined LiTEX (line time extension) that can actually extend the available row line time for adequate pixel charging. This approach based on the driving method is very desirable, because we can achieve higher resolution formats or larger display, even if the same

Design techniques of 2.25-in. diagonal poly-Si TFT-LCD panel for an HDTV/XGA projection system are described, especially focusing on the driver circuits. The area-efficiency of the driver circuits is a very important design issue, because the integrated poly-Si driver circuits takes a very large area due to inferior device characteristics of single crystal-Si transistors. For area-efficiency, the pixel with a novel structure of the line memory has been proposed, and the analog switch circuits ha

We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nod

In this paper, an image interpolation method based on even-odd decomposition (EOD) is proposed. An input signal for interpolation is decomposed to even and odd vectors by EOD. And then different interpolation methods are applied to even and odd vectors, respectively. This paper presents an analysis on the two vectors and new design methods for them. Also, based on the new design method, a signal flow graph of the proposed method is provided and compared with the CCI method in terms of complexity

To implement a compact and high-image-quality AMOLED mobile display, a previously proposed panel DAC concept was elaborated and improved. Three types of pixel structures for the panel DAC have been presented and discussed in terms of the yield, aperture ratio and timing margin. Also, the functional feasibility of the panel DAC has been verified by fabrication and measurement of low-temperature poly-Si TFT test circuits. The circuit area of the 8-bit DAC consisting of the 6-bit resistor-string-ba

Abstract OLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver

We have proposed novel pixel circuits and driving methods for a-Si TFT-LCDs that can reduce the numbers of both column and row lines to half of those of traditional a-Si TFT-LCDs for a given resolution format. Whereas one pixel of a traditional TFT-LCD is driven by a row line and a column line connected to the gate and the source of the thin film transistor respectively, the proposed novel TFT-LCD allows neighboring four pixels to share a gate line and a data line, thereby reducing the numbers o

This paper discusses an image quality issue of TFT-LCD monitors and televisions. To make jaggies invisible in TFT-LCD monitors, the resolution should be at least 200 pixels per inch (ppi), and the frame frequency of 120 Hz or even up to 240 Hz is used to express natural motion pictures in TFT-LCD televisions. The requirement of both high-resolution and high frame frequency decreases the available row line time, which necessarily leads to the insufficient pixel charging ratio. To address the insu

The concept of a counting-based digital-to-analog converter (CNT-DAC) is proposed to realize a compact column driver circuit for system-on-panel (SoP) applications. The traditional ramp DAC is very promising in the circuit-area respect, because it replaces the area-consuming read only memory (ROM)-type decoder with a counter; however, it is not widely used for display column drivers because it has several problems such as ramp signal distortion, charge sharing between column lines and pixel elec