신창환 교수

Because of the "Boltzmann tyranny" (i.e., the nonscalability of thermal voltage), a certain minimum gate voltage in metal-oxide-semiconductor (MOS) devices is required for a 10-fold increase in drain-to-source current. The subthreshold slope (SS) in MOS devices is, at best, 60 mV/decade at 300 K. Negative capacitance in organic/ferroelectric materials is proposed in order to address this physical limitation in MOS technology. Here, we experimentally demonstrate the steep switching behavior of a

A study of random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFET versus the planar bulk MOSFET is performed via atomistic 3D device simulation for devices with a 20 nm gate length. For identical nominal body and source/drain doping profiles and layout width, the trigate bulk MOSFET shows less threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) lowering and variation. RDF effects are found to be caused primari

Supercapacitors have shown great potential as a possible solution to the increasing global demand for next-generation energy storage systems. Charge repositioning is based on physical or chemical mechanisms. There are three types of supercapacitors-the electrochemical double layer, the pseudocapacitor, and a hybrid of both. Each type is further subdivided according to the material used. Herein, a detailed overview of the working mechanism as well as a new method for capacitance enhancement are p

A negative capacitance field‐effect transistor (FET) with sub‐60 mV/decade subthreshold slope (SS) at different temperatures (i.e. 14.8 mV/decade at 300 K, 15.7 mV/decade at 360 K and 24.3 mV/decade at 400 K) is experimentally demonstrated. A detailed account of the fabrication process of a negative capacitor is first introduced, followed by the measurement setup for the negative capacitance FET. The impact of temperature on negative capacitance FETs is investigated: (i) the equation for the int

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyze

Abstract In this study, a near‐infrared photodetector featuring a high photoresponsivity and a short photoresponse time is demonstrated, which is fabricated on rhenium diselenide (ReSe 2 ) with a relatively narrow bandgap (0.9–1.0 eV) compared to conventional transition‐metal dichalcogenides (TMDs). The excellent photo and temporal responses, which generally show a trade‐off relation, are achieved simultaneously by applying a p‐doping technique based on hydrochloric acid (HCl) to a selected ReSe

The endurance characteristic of Zr-doped HfO2 (HZO)-based metal–ferroelectric–metal (MFM) capacitors fabricated under various deposition/annealing temperatures in the atomic layer deposition (ALD) process was investigated. The chamber temperature in the ALD process was set to 120 °C, 200 °C, or 250 °C, and the annealing temperature was set to 400 °C, 500 °C, 600 °C, or 700 °C. For the given annealing temperature of 700 °C, the remnant polarization (2Pr) was 17.21 µC/cm2, 26.37 µC/cm2, and 31.8 µ

Feedback field-effect transistors (FBFETs) are devices based on a positive feedback loop in which the electrons and holes in the channel region act on the energy states of the potential barrier and wall. Owing to the positive feedback phenomenon, FBFETs have an excellent subthreshold swing (~0 mV/decade at 300 K), a high on-/off current ratio (~1010), and a clear saturation region. The power consumption of both the turn-on state and turn-off state is significantly low until operation commences.

The performance and threshold voltage variability of quasi-planar bulk MOSFETs are compared against those of conventional bulk MOSFETs, via three-dimensional (3-D) device simulations with gate line-edge roughness and atomistic doping profiles, at 25 nm gate length. The nominal performance of sixtransistor (6-T) SRAM cells is studied via 3-D simulation of full cell structures. Compact (analytical) modeling is used to estimate SRAM cell yields. As compared to conventional bulk CMOS technology, qua

In this work, the measured electrical characteristics of a fully depleted silicon-on-insulator (FDSOI) device and fin-shaped field-effect transistor (FinFET), whose gate electrode is connected in series to the bottom electrode of a ferroelectric capacitor (FE-FDSOI/FE-FinFET), are experimentally studied. The hysteretic property in input transfer characteristic of those devices is desirable for memory device applications, so that the understanding and modulating the hysteresis window is a key kno

Abstract In this work, the impact of fluorine (CF 4 ) and oxygen (O 2 ) plasma passivation on HfZrO x (HZO) based ferroelectric capacitor was investigated. By the fluorine passivation, the surface trap density and oxygen vacancies in the HZO-based Metal–ferroelectric–insulator–semiconductor (MFIS) capacitors were suppressed, resulting in the increased pristine remnant polarization (2P r ). The pristine value (2P r ) of baseline samples annealed at 500 °C and 600 °C were 11.4 µC/cm 2 and 24.4 µC/

Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three-dimensional (3-D) process and design simulations, transistor designs are optimized. Then