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We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state current can be enhanced by increasing the nanowire height, decreasing equivalent oxide thickness (EOT) or

Ion-sensitive field effect transistors have been advanced in recent years by utilizing silicon nanowires (Si-NWs), but establishing their optimized operation regime is an area of ongoing research. We propose a modified configuration of SiNWs in the form of a honeycomb structure to obtain high signal to noise ratio and high current stability. The low-frequency noise characteristics and the electrical stress are systematically considered for the optimization and compared against conventional SiNW

A silicon-based laser is a critical component in the realization of full silicon (Si) photonic integrated circuits due to advantages in cost-competitive integration with the mature digital technology. The poor optical gain stemming from the indirect energy band structure of Si, however, has been a hurdle to realize this goal. An efficient Si nanocavity can become a key enabler to overcome the hurdle by earning the interaction time for ephemeral photons. Here, we propose a weakly tapered Si nanop

Silicon nanowire has attracted considerable attention in thermoelectric devices because the diameter reduction can reduce thermal conductivity with boundary scattering, improving the figure of merit. Nevertheless, there are some challenges in device fabrication due to the relatively low efficiency and the difficulties in mass production. Here, we suggest the silicon nanowire with a corrugated surface to overcome these drawbacks by using a deep reactive-ion etcher. Corrugated silicon nanowires ca

The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on in

We performed 3D simulations to demonstrate structural effects in sub-20 nm gate-all-around silicon nanowire field effect transistors having asymmetric channel width along the channel direction. We analyzed the differences in the electrical and physical properties for various slopes of the channel width in asymmetric silicon nanowire field effect transistors (SNWFETs) and compared them to symmetrical SNWFETs with uniform channel width. In the same manner, the effects of the individual doping conc

Abstract A drain-extended fin field-effect transistor (FinFET) with a dual material gate (DMG) and a high- k field plate (FP), named DF-DeFF, is proposed for high-voltage radio frequency (RF) applications. The FP induces the charge variation in the drain extension, which appears as either the extended depletion in the gate-off state or the electron accumulation in the gate-on state. Along with the FP, the DMG forms a step-like potential variation along the channel, which leads to electron accele

We demonstrate a highly biomimetic spiking neuron capable of fast and energy-efficient neuronal oscillation dynamics. Our simple neuron circuit is constructed using silicon-germanium heterojunction based bipolar transistors (HBTs) with nanowire structure. The HBT has a hysteresis window with steep switching characteristics and high current margin in the low voltage range, which enables a high spiking frequency (~ 245 kHz) with low energy consumption (≤ 1.37 pJ/spike). Also, gated structure achie

Modeling capabilities and considerations to achieve a unified reliability model (URM) are addressed. The causes of the trap generation and their effects on the device characteristics serve the unified reliability model. A strategy taken in the SNU group based on the CLESICO system is introduced, where the hydrogen transport and trapping in the gate dielectric to form active carrier trapping sites and their effects on the device characteristics such as the current degradation are treated in a sys