김건환 교수

Abstract Various array types of 1‐diode and 1‐resistor stacked crossbar array (1D1R CA) devices composed of a Schottky diode (SD) (Pt/TiO 2 /Ti/Pt) and a resistive switching (RS) memory cell (Pt/TiO 2 /Pt) are fabricated and their performances are investigated. The unit cell of the 1D1R CA device shows high RS resistance ratio (≈10 3 at 1.5 V) between low and high resistance state (LRS and HRS), and high rectification ratio (≈10 5 ) between LRS and reverse‐state SD. It also shows a short RS time

Abstract Conventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf 0.8 Si 0.2 O 2 /Al 2 O 3 /Hf 0.5 Si 0.5 O 2 )-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 10 4 ), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 μs), (v) excellent

Memristor-integrated passive crossbar arrays (CAs) could potentially accelerate neural network (NN) computations, but studies on these devices are limited to software-based simulations owing to their poor reliability. Herein, we propose a self-rectifying memristor-based 1 kb CA as a hardware accelerator for NN computations. We conducted fully hardware-based single-layer NN classification tasks involving the Modified National Institute of Standards and Technology database using the developed pass

A modified biasing scheme was adopted to improve the electrical endurance characteristics of conducting filamentary resistive switching (RS) in a Pt/TiO2/Pt RS cell. The modified bias scheme included the application of bias voltages with alternating polarity, even though RS proceeds in non-polar mode, which results in the stable distribution of each resistance states as well as improved endurance. This was attributed to the minimized consumption of oxygen ions in the TiO2 film, which can be indu

Kirchhoff's law was used to examine the electrical specifications of selection diodes, which are essential for suppressing the read interference problems in nano-scale resistive switching cross bar arrays with a high block density. The diode in the cross bar array with a 100 Mb block density should have a reverse/forward resistance ratio of > 10(8), and a forward current density of > 10(5) A cm(-2) for stable reading and writing operation. Whilst normal circuit simulators are heavily overloaded

/TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to s

A Schottky diode (SD) with Au/Pt/TiO2/Ti/Pt stacked structure were fabricated for its application to crossbar type resistive switching (RS) memory. The SDs showed a highly promising rectification ratio (∼2.4 × 106 @ ±2 V) between forward and reverse state currents and a high forward current density (∼3 × 105 A/cm2 @ 2 V), which is useful for highly integrated crossbar RS memory. The SD has local forward current conduction paths, which provides extremely scaled devices with an advantage. The mini

The effects of the external load resistance on the resistive switching (RS) behavior of RS cells were examined using model calculations and experiments. With increasing load resistance, the reset voltage increased more rapidly than the set voltage, which eventually resulted in RS failure. For the experiment, various electrode materials were examined to achieve both a stable RS behavior of a film and a cross bar array (CBA) with sufficiently low line resistance. The effect of the line resistance

Abstract In this study, highly reliable and accurate weight‐modification behaviors are realized using a W/Al 2 O 3 (3 nm)/HfO 2 (7 nm)/TiN memristive device. The accuracy of the simulated inference of the MNIST dataset when considering the weight‐modification behavior is ≈95%. It is determined the optimal programming voltage pulsing conditions considering i) a high linearity in the weight‐modification, ii) symmetry between potentiation and depression, and iii) an alleviation of the voltage‐drivi

Abstract As a selection device for highly integrated crossbar‐type data storage, the chalcogenide‐based ovonic threshold switch (OTS) shows high selectivity, fast switching speed, and bi‐directional operation ability for stacking with versatile memory devices. These promising performance features of OTS are based on electronic resistance switching through the amorphous chalcogenide active layer. However, there is a need to improve the thermal stability of the chalcogenide material, which is esse

Fully "Erase-free" multi-bit operation was demonstrated in a W/HfO₂/TiN-stacked resistive switching device. The term Erase-free means that a digital state in a multi-bit operation can be achieved without initializing the device resistance state when the device moves to another digital state. Because initializing the resistance state of a resistive switching device causes high energy consumption, omitting this sequence can achieve energy efficient multi-bit operation during rewriting o

Abstract Here, an optimized method for energy‐efficient and highly reliable multibit operation in a Au/Al 2 O 3 /HfO 2 /TiN resistive switching (RS) device is investigated. A thin Al 2 O 3 layer inserted between the top electrode and the HfO 2 RS layer in a capacitor‐like RS device plays the role of an electrical resistor and modulates the external bias‐dependent resistance variation behavior of the RS device. Compared to the case where a single HfO 2 layer is used, the device with a Al 2 O 3 /H