정한울 교수

When the input voltage difference of a sense amplifier (SA) exceeds the offset voltage (VOS), the SA correctly detects it and outputs a large signal. However, when the input voltage is in a certain region, the SA can fail to sense the input voltage difference even if it is sufficiently large. This input voltage region is defined as the sensing dead zone of the SA. Because sensing dead zones differ depending on SAs and the input voltages to the SA differ depending on the memory devices, analyzing

This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations. The proposed 9T SRAM cell uses bit interleaving to achieve soft error immunity and utilizes a column-based virtual VSS signal to eliminate unnecessary bitline discharges in the unselected columns, thereby reducing the energy consumption. In a 22-nm FinFET technology, the proposed PG9T SRAM ce

A novel high-speed and highly reliable sense-amplifier-based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) operation. The SAFF-TCD adopts the internally generated detection signal to indicate the completion of sense-amplifier stage transition. The detection signal gates the pull-down path of the sense-amplifier stage and the slave latch, thus

Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability of static random access memory (SRAM) cells. This paper proposes an NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting the path from the bit-line to the cross-coupled inverter pair using the transmission gate. In the proposed 7T SRAM cell, the half-select issue is resolved, meaning that no write-back operation i

A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show th

An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energ

We have proposed a current mirror-based level shifter (LS) with a logic error detection (CMLS-LED), which is capable of converting a near-threshold signal to a super-threshold signal. The proposed CMLS-LED resolves the current contention problem observed in the conventional cross-coupled pFET-based LS (CPLS) by using the current mirror and removes the static current in the conventional current mirror LS with adopting the feedback pFET controlled by the output node. Compared with Wilson's current

We have demonstrated fully integrated 64-kb magnetoresistive random access memory (MRAM) using 0.24-/spl mu/m CMOS technology and discussed some key issues in process integration. Optimal tunneling magnetoresistive (TMR) properties of MRAM bits (37% of TMR ratio and 5-10 k/spl Omega//spl middot//spl mu/m/sup 2/ of RA) were obtained mainly by the control of bottom electrode roughness, and electrical shorting was avoided by some commercialized wet solutions. In viewpoint of process integration, ex

The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL volta

An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS du

A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and

A trip-point bit-line precharge (TBP) sensing scheme is proposed for high-speed single-ended static random-access memory (SRAM). This TBP scheme mitigates the issues of limited performance, power, sensing margin, and area found in the previous single-ended SRAM sensing schemes by biasing the bit-line to a slightly larger value than the trip point of the sense amplifier. Simulation results show that the TBP sensing scheme can reduce the sensing time by 58.5% and 10% compared with the domino and a

In this brief, an energy-efficient, wide-range level shifter (LS) with a logic error detection circuit (LEDC) is proposed. The proposed LS is designed based on a current mirror-based LS (CMLS), and a feedback pFET is added to solve the static current, which is a limitation of the CMLS. Similarly, Wilson’s CMLS (WCMLS) solves the problem of the CMLS through the feedback pFET; however, it cannot convert low supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink

Bitline (BL) charge-recycling-based static random access memory (SRAM) write assist circuits (BCR-WA) are proposed to reduce the minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ) of SRAM. In the proposed schemes, the charges stored on the unselected BL are utilized to raise the cell ground voltage (VSS) of the selected bit cell, and the increased cell VSS (CVSS) enhances the write ability. According to the meta

A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline pr