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An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 μW to continue t

To address the increasing demand for high-bandwidth mobile communications, 5G technology is targeted to support data-rates up to 10Gb/s. To reach this goal, one of challenging tasks for wireless transceivers is to generate millimeter-wave (mmW) band Lo signals that have an ultra-low integrated phase noise (IPN). The IPN of an LO signal should be reduced to less than -30dBc to satisfy the EVM requirements of high-order modulations, such as 64-QAM. Figure 23.1.1 shows the frequency spectrum for ce

The generation of mm-wave (mmW) signals that have ultra-low phase noise (PN) is very important for the design of RF transceivers (TRXs) for high-data-rate 5G systems. Direct-RF-sampling TRXs also require high-frequency clock signals, having extremely low integrated PN (IPN) [1]. To satisfy such stringent noise requirements, the rms jitter of mmW-band signals must be reduced to sub-100fs. Recently, a charge-pump (CP) PLL in [1] achieved a very low rms jitter of less than 60fs at 14GHz. However, t

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital S

A wideband inductance-capacitance voltage-controlled oscillator (VCO) with a g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -switching technique was designed and fabricated in the 65-nm CMOS process. With a switchable secondary gate-biased active core and a primary core, the VCO operates in two different modes. In the LF mode, in which switches turn on the secondary core, the increased start-up gain facilitates LF oscillation. In the HF m

A wideband and low phase noise quadrature local oscillation (LO) signal generator for multistandard cellular transceivers was proposed. Using the new LO-plan consisting of divide-by-6, divide-by-4, and divide-by-12 frequency dividers, the required frequency-tuning range (FTR) of a voltage-controlled oscillator (VCO) was reduced to 39%, which can be easily covered by a single LC-VCO. Due to the reduced FTR, the VCO can retain a high Q-factor and achieve low phase noise. The key building block of

To meet requirements of high data-rates, RF transceivers for a 5G standard must have an ultra-wide bandwidth in a mm-wave band. A big challenge of a 5G transceiver is to generate ultra-low-PN (phase noise) local-oscillator (LO) signals to suppress integrated PN (IPN) over such an extremely wide bandwidth. A PLL that directly generates mm-band LO signals is not a good choice due to power-hungry frequency dividers and relatively poor PN. An mm-band LO generator, cascading a GHz-range PLL and a fre

As the utilization of the mm-wave spectrum becomes active, designers' interests are shifting to even higher frequencies in the W-band. Given their potential use as carrier frequencies for the next-generation mobiles (i.e., beyond 5G), these W-band signals must have ultra-low phase noise (PN). Currently, the most popular solution to generate such frequencies is with a cascaded architecture: a first-stage PLL generates a low-PN signal at a relatively low frequency at which the VCO LC tank has a hi

This work presents a 12-to-14.5GHz SSPLL, robust to frequency disturbances with a wide lock -in range. The proposed f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -correcting loop (FCL) generates a new signal of S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">us</sub> with unevenly spaced edges that are adaptively aligned with the zero crossing points of the output signal of the SSPLL, S ou

This paper presents a low-jitter, injection-locked frequency generator that can provide multiple output frequencies concurrently. The injection-locked digitally controlled oscillators (DCOs) can be controlled separately so that their output frequencies can be changed independently between 0.9 and 1.2 GHz in 15-MHz steps. Due to the proposed time-interleaved frequency calibrator that operates continuously in the background, all injection-locked DCOs are ensured to maintain excellent jitter perfor

This paper presents a low-reference-spur and low-jitter injection-locked clock multiplier (ILCM). To secure these performances over PVT-variations, we propose the use of a voltage-domain period-calibrating loop (VDPCL) in the ILCM that monitors the intrinsic period of the VCO and stores this information as the charges in a capacitor. By evaluating the voltage of the capacitor, it is possible to correct the free-running frequency of the VCO. By iteratively accumulating charges, the precision of t

This work presents a D-band frequency synthesizer that can generate an ultra-low jitter output signal over a large frequency-tuning range (FTR). To overcome the structural limitations of conventional sub-terahertz (sub-THz) frequency synthesizers and concurrently achieve a low jitter and a large FTR, we designed a two-stage architecture, in which a 50-GHz band subsampling PLL (SSPLL) with a 3rd-harmonic (HM)-rich class-F voltage-controlled oscillator (VCO) in the first stage interoperated with a

An area-efficient CMOS cross-coupled LC-VCO, operating from 5.74 GHz to 8.02 GHz and featuring a tail noise filter with two tail inductors integrated inside the main inductor, is presented for the first time. The tail noise filter comprised two nested intertwined tail inductors (NITIs) and a tail capacitor bank, effectively suppressing phase noise (PN) while generating negligible magnetic couplings between the main inductor and the NITIs. The proposed architecture enables area-efficient CMOS cro

This work presents a low-phase noise (PN) mm-wave injection-locked frequency multiplier (ILFM) using an ultra-low power frequency-tracking loop (FTL). Monitoring the averages of phase deviations rather than detecting the instantaneous values, the FTL consumed only 600W to calibrate the mm-wave ILFM generating a frequency between 27 and 30GHz. While consuming low power, the proposed FTL effectively regulated the PN degradation, which was less than 2dB up to 100MHz offset across VT variations.

This work presents a low-phase noise (PN) mm-wave injection-locked frequency multiplier (ILFM) using an ultra-low power frequency-tracking loop (FTL). Monitoring the averages of phase deviations rather than detecting the instantaneous values, the FTL consumed only 600W to calibrate the mm-wave ILFM generating a frequency between 27 and 30GHz. While consuming low power, the proposed FTL effectively regulated the PN degradation, which was less than 2dB up to 100MHz offset across VT variations.