정재웅 교수

A quantum confined transport based on a zinc oxide composite nanolayer that has conducting states with mobility edge quantization is proposed and was applied to develop multi-value logic transistors with stable intermediate states. A composite nanolayer with zinc oxide quantum dots embedded in amorphous zinc oxide domains generated quantized conducting states at the mobility edge, which we refer to as "mobility edge quantization". The unique quantized conducting state effectively restricted the

A biosensor is defined as a measuring system that includes a biological receptor unit with distinctive specificities toward target analytes. Such analytes include a wide range of biological origins such as DNAs of bacteria or viruses, or proteins generated from an immune system of infected or contaminated living organisms. They further include simple molecules such as glucose, ions, and vitamins. One of the major challenges in biosensor development is achieving efficient signal capture of biolog

We report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by a block copolymer self-assembly process. Optimized surface functionalization provides stacking structures of Si-containing block copolymer thin films to generate uniform memristor device structures. Both the silicon oxide film and nanodot memristors, which were formed by the plasma oxidation of the self-assembled block copolymer thin films, presented unipolar switching behaviors with appropriat

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high-κ/metal-gate technology. Through analytical device modeling on BTBT and subthreshold current, static noise margin (SNM), off

High environmental stability of organic field-effect transistors is achieved by the use of conjugated polymer/paraffin blends.

We report world’s first demonstration of n- and pMOSFET in 3-Dimensional Stacked FET (3DSFET) with vertically stacked n/p metal gate and isolated source/drain between top and bottom FETs. We proved the possibility of 3DSFET with respect to area scaling not only by vertically stacking but also by reducing gate pitch down to 45 nm, which is the smallest dimension reported so far in 3DSFETs. The electrical properties of top/bottom placement has been studied to guide 3DSFET scheme design. Moreover,

Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuit designs. We design a novel ternary multiplier based on a ternary CMOS (T-CMOS) compact model. To estimate performance and energy efficiency of our ternary design, we construct a standard ternary-cell library and exploit a ternary static timing analysis (

Charge transport in π-conjugated polymer films involves π-π interactions within or between polymer chains. Here, we demonstrate a facile solution processing strategy that provides enhanced intra- and interchain π-π interactions of the resultant polymer films using a good solvent additive with low volatility. These increased interactions result in enhanced charge transport properties. The effect of the good solvent additive on the intra- and intermolecular interactions, morphologies, and charge t

The operational space formulation (OSF) has been enhanced from a practical viewpoint through the application of the time-delay estimation (TDE). In principle, the OSF enables an excellent decentralized control owing to its ability to achieve dynamic consistency. In reality, however, it can suffer from modeling errors and relatively large computational demands. As a remedy for these problems, the OSF has been combined with the TDE, which is known for its accurate estimation of robot dynamics with

In this study, we have demonstrated 3-Dimensional Stacked FET (3DSFET) with Self-Aligned Direct Back-side Contact (SA-DBC) and Back-side Gate Contact (BGC) in 48nm gate pitch, which is the smallest dimension and the world's first demonstration reported so far. Simultaneous threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{t})$</tex> targeting for both n- and pFET in common gate and n/p-connection with vertical common contact wer

Long-range alignment of conjugated polymers is as critical as polymer chain packing for achieving efficient charge transport in polymer thin films used in electronic and optoelectronic devices. Here, the present study reports a facile, scalable strategy that enables the deposition of macroscopically aligned polymer semiconductor nanowire (NW)-array films with highly enhanced charge carrier mobility, using a modified controlled evaporative self-assembly (MCESA) technique. Organic field-effect tra