권지민 교수
Ji-Min Kwon
KAIST 전기및전자공학부 · 공학
연구실 소개
권지민 교수의 연구실은 고주파·고성능 무선 통신 시스템을 위한 밀리미터파 및 서브테라헤르츠 대역의 통합 반도체 소자 기술과, 차세대 메모리 및 로직 소자에 적합한 2차원 물질 및 산화막 반도체 기반 나노소재 기반의 3D 통합 기술을 핵심 연구 분야로 삼고 있습니다. 특히, 유리 기반의 저손실 통합 플랫폼, In₂Se₃와 같은 2차원 페로일렉트릭 물질의 웨이퍼스케일 성장, 그리고 아토믹 레이어 디포지션을 활용한 고밀도 메모리 소자 설계에 주력하고 있습니다. 이와 함께, 탄소나노튜브 및 2차원 반도체를 활용한 고성능 3D 통합 회로 기술과 대량 데이터 기반의 전기적 특성 분석 프레임워크 개발도 진행 중입니다.
연구 현황
연구 성과 추이
표시된 성과는 수집된 데이터 기준으로 산출되며, 일부 차이가 있을 수 있습니다.
주요 논문
7The growing demand for sub-THz wireless systems requires not only high-frequency RF devices but also compact, low-loss integration platforms. In this work, we demonstrate a monolithic III-V/glass RF platform using a low-temperature wafer bonding technique, where III-V enables high-frequency transistors and glass offers a low-loss, low-cost, and dimensionally stable platform. The InGaAs HEMTs fabricated on a glass substrate achieve f<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink=
Two-dimensional (2D) indium selenide (In2Se3) has great potential for next-generation processing-in-memory applications owing to high intrinsic carrier mobility and strong ferroelectricity. However, the lack of wafer-scale, back-end-of-line (BEOL) compatible growth and inherent polarization-induced hysteresis limit their viability in logic circuits. Here, we report thermal evaporation of a non-ferroelectric κ-phase In2Se3 film that forms uniformly over 4-inch wafer-scale at <450 °C. Structural c
ABSTRACT Monolithic three‐dimensional integration demands embedded memory technologies that achieve extreme density scaling under limited back‐end‐of‐line thermal budget. Atomic layer deposition‐grown amorphous oxide semiconductors (AOS) are attractive for this purpose because of their excellent conformality and intrinsically low off‐state current I OFF, enabling vertical channel transistors (VCTs) for capacitor‐less gain‐cell memory operation. However, in VCT, oxygen‐deficient AOS channels requ
ABSTRACT Atomically thin 2D semiconductors enable excellent electrostatic control even in highly scaled transistors with few‐nanometer gate lengths. The electrical characteristics of 2D transistors can vary significantly with the number of layers, yet how device behavior evolves with channel thickness remains statistically unexplored. This limitation mainly arises from the difficulty of obtaining large numbers of single‐crystal flakes with well‐controlled thickness and fabricating devices. Here,
Single-Flake Transistor In the Research Article (DOI: 10.1002/adfm.202532204), Yongwoo Lee, Haksoon Jung, Jimin Kwon, and co-workers demonstrate that 3-8 layer MoS2 flakes can be reliably classified using pixel intensity contrast in the red, green, and blue optical channels. This approach enables large-scale correlation between optically identified layer number and electrical characteristics, providing a foundation for statistically resolving thickness-dependent electrical behavior in 2D transis
This study presents a benchmark framework for digital blocks featuring an active backside clock distribution network (BSCDN), which incorporates clock buffers and sinks implemented using backside-compatible logic based on carbon nanotube field-effect transistors (CNFETs). The proposed framework includes the fabrication, characterization and TCAD modeling of complementary CNFETs, neural network-based compact modeling, standard cell characterization, and a block-level benchmark comparing the perfo
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