이준열 교수

A referenceless single-loop clock and data recovery (CDR) with a 6.4-11-Gb/s capture range is presented. A dynamic bandwidth control (DBWC) technique for reducing the frequency-acquisition time and adaptive loop gain control (ALGC) for optimizing the jitter tolerance are described in detail. In addition, a cycle-slip detector (CSDET) with a consecutive-edge selector (CES) is proposed to improve the accuracy of the frequency detection. Fabricated in a 28-nm CMOS process, the proposed CDR has a fr

This paper describes a ground-referenced signaling (GRS) transceiver with a 3-tap feed-forward equalizer and low frequency mode. In the prototype transceiver, four DQ data lanes share one DQS clock-forwarding lane. To accommodate dynamic voltage and frequency scaling, the proposed transmitter operates in two modes depending on the frequency. The feed-forward equalizer's tap coefficients can be tuned by the pre-charged voltage levels and the number of activated segments. Fabricated in a 28-nm CMO