박관서 교수

This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed ope

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign-sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-p

A single-loop referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is proposed that tracks the frequency difference by detecting the drift direction of the non-return to zero bit stream with respect to the multi-phase clock and generates UP/DN output signals accordingly. When frequency locked, the BBPFD is degenerated into the conventional bang-bang phase detector (BBPD). The UP/DN output signals from t

A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented. The proposed frequency detector (FD) is derived from a multi-phase oversampling FD. Through accurate analysis of the root causes limiting the capture range, the extension techniques are proposed and digitally implemented by a small hardware overhead. The FD achieves the unlimited frequency detection capability and exhibits robust operation regardless of the initi

To meet the demand for high memory bandwidth, high-bandwidth memory (HBM) uses a silicon interposer technology to increase the number of I/O pins. Interfaces with the silicon interposer provide a higher throughput (Gb/s/μm) than other packaging technologies due to the high channel density. To increase the throughput further, either the per-pin data rate or the channel density should be increased. Since increasing the per-pin data rate requires a complex and power-hungry circuitry, increasing the

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/dr

The ever-expanding demand for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1]-[4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture.

Continuous-rate referenceless clock and data recovery (CDR) circuits are capable of operating over a wide range of data rates in multiple standards. To achieve wide-range operation without an external reference clock, several frequency detection techniques are presented [1]-[5]. However, most of the previous techniques require considerable hardware and power overhead to obtain information for frequency detection. It leads to a performance tradeoff between capture range, lock time, and power cons

This article presents design techniques for a continuous-rate reference-free clock and data recovery (CDR) circuit employing a stochastic frequency–phase detector (SFPD). By taking a histogram-based design methodology, optimal weights for both frequency and phase detection are obtained by utilizing the same information as the Alexander phase detector. The design methodology is inductive and stochastic, distinguished from the conventional, deductive, and procedural methods. To verify a robust ope

This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by

This brief presents a 1.62-to-10-Gb/s receiver for next generation video interconnected with an adaptive decision-feedback equalizer (DFE). The adaptive DFE facilitates the best bit error rate (BER) performance for various losses of video cables. A differential-pair stage is added to the DFE for extending an effective DFE range, presetting a minimum data level, and calibrating a mismatch offset. Circuit techniques are proposed to relax timing constraints for the direct-feedback DFE architecture.

This article presents design techniques for a PAM-4 baud-rate digital clock and data recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate phase detector (PD) is designed in an inductive and stochastic way, so there is a clear difference from the existing deductive and logical method used in sign-sign Mueller–Müller PD (SS-MMPD), a representative baud-rate PD. By collecting the histograms of the sequential PAM-4 patterns under EARLY and LATE sampling phases a

This brief presents an 8-to-16-Gb/s referenceless receiver with a stochastic continuous-time linear equalizer (CTLE) adaptation. The proposed stochastic CTLE gain selector (SCGS) achieves a maximum horizontal eye margin and avoids sub-optimal settling by utilizing sequential edge and data samples. The proposed SCGS detects the optimum CTLE coefficient with the weighted summation of the histograms obtained under various data patterns and channel conditions. The stochastic CTLE adaptation shares t

Supporting a wide operating range for industrial-standard backward-compatible transmitters often results in energy inefficiency. This paper describes an energy-efficient voltage-mode-serializing transmitter with an operating range of up to 32 Gb/s. The proposed transmitter uses a programmable internal supply to set the voltage level for various data rates optimally, thus improving overall energy efficiency. Output swing and pre-emphasis levels are largely adjustable while the constant output imp