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Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

A 1.1-GHz fractional-N frequency synthesizer is implemented in 0.5-/spl mu/m CMOS employing a 3-b third-order /spl Delta//spl Sigma/ modulator. The in-band phase noise of -92 dBc/Hz at 10-kHz offset with a spur of less than -95 dBc is measured at 900.03 MHz with a phase detector frequency of 7.994 MHz and a loop bandwidth of 40 kHz. Having less than 1-Hz frequency resolution and agile switching speed, the proposed system meets the requirements of most RF applications including multislot GSM, AMP

Fractional-N frequency synthesis based on /spl Delta//spl Sigma/ modulators offers wide bandwidth with narrow channel spacing and alleviates PLL design constraints for phase noise and reference spur. However, the synthesizer phase noise performance is significantly affected by the high-frequency out-of-band noise, which is difficult to suppress with the finite number of PLL loop filter poles. This work uses a 3b 3rd-order modulator that generates less high-frequency noise and makes the system le

Fractional-N frequency synthesis relaxes the phase-locked loop (PLL) design constraints to achieve a low noise performance while providing the same channel spacing. Inherent spurs generated by this system can be reduced with various techniques. The proposed architecture effectively compensates the periodic phase error in the time domain so that it is useful with widely used charge-pump PLLs. An on-chip tuning by a delay-locked loop (DLL) is also provided to make the system less dependent on the

A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-/spl mu/m 25-GHz BiCMOS. A /spl Delta//spl Sigma/ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip /spl Delta//spl Sigma/ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling a

A low power CMOS voltage-controlled oscillator (VCO) is presented. Its simple and symmetric structure can provide low-power and low-noise operation, which is comparable to existing architectures in CMOS. The proposed VCO is digitally programmable to have different center frequencies while maintaining its linear voltage-to-frequency characteristic and a desirable VCO gain at tuned frequency. Simulation result shows that the output frequency of 1 GHz is achieved at the power consumption of 3.5 mW.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <?Pub Dtl=""?>This paper describes experimental approaches to analyze the effect of the substrate noise on phase-locked loop (PLL) performance. Spectral analysis considering noise transfer functions of the PLL is used to identify the substrate-noise sensitive components of the PLL. Analyzing the sidebands seen in a spectrum analyzer confirms the importance of knowing the PLL loop dynamics and noise t

A 1-GHz phase-locked loop (PLL) is implemented in 0.5-/spl mu/m CMOS to generate a 500-MHz clock with 50% duty. The voltage-controlled oscillator (VCO) combined with the differential charge pump is employed to have low clock skew and better immunity to the noises from supply, ground and substrate. The long-term peak-to-peak jitter of less than 70 psec and 165 psec are achieved for the quiet supply line and for the noisy one modulated by 400-mV/sub p-p/, 500-kHz square wave, respectively. The pro

Ultra-wideband (UWB) technology has received great attention in recent short-range communication systems and been considered one of the potential candidates for upcoming IEEE 802.15.6 body area network (BAN) standard. High penetration capability and high precision ranging with a wide bandwidth of up to 7.5GHz (from 3.1GHz to 10.6GHz) make it easy to image the organs of human body for biomedical applications. In addition, low electromagnetic radiation less than -41.3dBm/MHz is safe for human tiss

A 4.75 to 6.1 GHz PLL with uniform bandwidth control is implemented in 90 nm CMOS. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, the proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable PLL bandwidths such as PCI Express Gcn2 or FB-DIMM applications. This work also addresses noise and coupling aspects in dual-path VCO design. The measurement results show that

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a △Σ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the △Σ fractional-N PLLs are discussed with simulation and hardware results. High-order △Σ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for

A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 /spl mu/m CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.

Fractional-N frequency synthesis provides agile switching in narrow channel spacing systems and alleviates phase-locked loop (PLL) design constraints for phase noise and reference spur. The inherent problem of the fractional-N frequency synthesizer is that the periodic operation of the dual-modulus divider produces spurious tones. Several techniques have been used to reduce spurious tones. Among those techniques, the delta-sigma modulation method provides arbitrarily fine frequency resolution an

An all‐digital PLL (ADPLL) which employs a ΔΣ delay‐locked loop (DLL) to achieve a PVT‐insensitive time resolution of the time‐to‐digital converter (TDC) as well as noise‐shaped dithering is implemented in 65 nm CMOS. Experimental results show that the proposed method can achieve spur reduction with slight degradation of in‐band phase noise. The 1.8 GHz ADPLL consumes 14.3 mW, while the TDC with the ΔΣ DLL consumes 2.1 mW.

A coarse‐fine dual‐loop digital low dropout regulator (DLDO) having a binary weighed transistor array in the coarse loop and a 1‐bit ΔΣ modulator in the fine loop is proposed. Compared with the conventional DLDO, the proposed architecture significantly reduces hardware complexity and alleviates matching requirement, enabling a robust DLDO design for low‐voltage phase‐locked loops. The proposed DLDO designed in 65 nm CMOS generates a noise‐shaped output voltage whose peak value is &lt;1 mV with t