이영주 교수

Hybrid electric vehicle (HEV) technology provides an effective solution for achieving higher fuel economy, better performance, and lower emissions, compared with conventional vehicles. Plug-in HEVs (PHEVs) are HEVs with plug-in capabilities and provide a more all-electric range; hence, PHEVs improve fuel economy and reduce emissions even more. PHEVs have a battery pack of high energy density and can run solely on electric power for a given range. The battery pack can be recharged by a neighborho

With the advent of battery-powered portable devices and mandatory adoption of power factor correction, noninverting buck-boost converters are garnering lots of attention. Conventional two-switch or four-switch noninverting buck-boost converters choose their operation modes by measuring input and output voltage magnitude. The criterion for the selection of the operation mode can cause higher output voltage transients in the neighborhood, where input and output are close to each other. For the mod

A highly efficient and novel control strategy for improving the transients in the output voltage of a DC-DC positive buck-boost converter, required for low-power portable electronic applications, is presented in this paper. The proposed control technique can regulate the output voltage for variable input voltage, which is higher, lower, or equal to the output voltage. There are several existing solutions to these problems, and selecting the best approach involves a tradeoff among cost, efficienc

Feature detection is important in various mesh processing techniques, such as mesh editing, mesh morphing, mesh compression, and mesh signal processing. In spite of much research in computer vision, automatic feature detection even for images still remains a difficult problem. To avoid this difficulty, semi-automatic or interactive techniques for image feature detection have been investigated. In this paper, we propose a geometric snake as an interactive tool for feature detection on a 3D triang

Solid-state drives (SSDs), built with many flash memory channels, is usually connected to the host through an advanced high-speed serial interface such as SATA III associated with a transfer rate of 6Gb/s [1–2]. However, the performance of SSD is in general determined by the throughput of the ECC blocks necessary to overcome the high error-rate [3]. The binary BCH code is widely used for the SSD due to its powerful error-correction capability. As it is hard to achieve high-throughput strong BCH

This brief presents an area-efficient tree architecture for finding the first two minima as well as the index of the first minimum, which is essential in the design of a low-density parity-check decoder based on the min-sum algorithm. The proposed architecture reduces the number of comparators by reusing the intermediate comparison results computed for the first minimum in order to collect the candidates of the second minimum. As a result, the proposed tree architecture improves the area-time co

With the advent of battery-powered portable devices and the mandatory adoptions of power factor correction (PFC), non-inverting buck-boost converter is attracting numerous attentions. Conventional two-switch or four-switch non-inverting buck-boost converters choose their operation modes by measuring input and output voltage magnitudes. This can cause higher output voltage transients when input and output are close to each other. For the mode selection, the comparison of input and output voltage

This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequen

To improve the reliability of MLC NAND flash memory, this paper presents an energy-efficient high-throughput architecture for decoding concatenated-BCH (CBCH) codes. As the data read from the flash memory is hard-decided in practical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capability and energy efficiency. In the proposed CBCH decoding, the number of on-chip memory accesses consuming much energy is minimized by computing and u

To achieve a high-throughput decoder, massive-parallel computations are normally applied to the Chien search, but the parallel realization increases the hardware complexity significantly. To reduce the hardware complexity of the parallel Chien search, this brief proposes a 2-D optimization method. In contrast to the previous 1-D optimizations, the proposed method maximizes the sharing of common subexpressions in both the row and column directions. All the partial products needed in the parallel

This paper presents an approximate computing method of long short-term memory (LSTM) operations for energy-efficient end-to-end speech recognition. We newly introduce the concept of similarity score, which can measure how much the inputs of two adjacent LSTM cells are similar to each other. Then, we disable the highly-similar LSTM operations and directly transfer the prior results for reducing the computational costs of speech recognition. The pseudo-LSTM operation is additionally defined for pr

In general, the interleaved structures in boost converters are able to reduce input current ripple and output voltage ripple leading to smaller size of input/output filters, to have fault tolerance, to take higher bandwidth, and to minimize EMI from reverse recovery current in output rectifier by adopting discontinuous inductor current mode in each interleaved converter. In this paper, a phase shift switching scheme of paralleled switches for boost converter is proposed in which one inductor, tw