[Paper Review] 2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Deep Learning Architecture (DLA) onto FPGA Boards

Tolulope A. Odetola, Katie M. Groves+1 more|arXiv (Cornell University)|Nov 14, 2019

VLSI and Analog Circuit Testing26 references6 citations

TL;DR

This paper proposes a novel 2L-3W (2-Level 3-Way) hardware-software co-verification methodology for mapping deep learning architectures (DLAs) onto FPGA boards, enabling layer-by-layer cross-paradigm verification across software (Caffe), high-level synthesis (Vivado HLS), and hardware (PYNQ FPGA). The method uses automated Python-based similarity scoring to validate implementation correctness, achieving 99% layer-wise similarity in design stages and identifying mapping issues early, with results demonstrating high fidelity and debuggability in DLA deployment on FPGAs.

ABSTRACT

FPGAs have become a popular choice for deploying deep learning architectures (DLA). There are many researchers that have explored the deployment and mapping of DLA on FPGA. However, there has been a growing need to do design-time hardware-software co-verification of these deployments. To the best of our knowledge this is the first work that proposes a 2-Level 3-Way (2L-3W) hardware-software co-verification methodology and provides a step-by-step guide for the successful mapping, deployment and verification of DLA on FPGA boards. The 2-Level verification is to make sure the implementation in each stage (software and hardware) are following the desired behavior. The 3-Way co-verification provides a cross-paradigm (software, design and hardware) layer-by-layer parameter check to assure the correct implementation and mapping of the DLA onto FPGA boards. The proposed 2L-3W co-verification methodology has been evaluated over several test cases. In each case, the prediction and layer-by-layer output of the DLA deployed on PYNQ FPGA board (hardware) alongside with the intermediate design results of the layer-by-layer output of the DLA implemented on Vivado HLS and the prediction and layer-by-layer output of the software level (Caffe deep learning framework) are compared to obtain a layer-by-layer similarity score. The comparison is achieved using a completely automated Python script. The comparison provides a layer-by-layer similarity score that informs us the degree of success of the DLA mapping to the FPGA or help identify in design time the layer to be debugged in the case of unsuccessful mapping. We demonstrated our technique on LeNet DLA and Caffe inspired Cifar-10 DLA and the co-verification results yielded layer-by-layer similarity scores of 99\% accuracy.

Motivation & Objective

• To address the lack of comprehensive design-time verification in DLA mapping to FPGAs, particularly for layer-by-layer correctness across software, hardware design, and deployed hardware.
• To develop a systematic methodology that enables early detection of implementation errors during the DLA-to-FPGA mapping process.
• To provide a scalable, automated verification framework that supports cross-paradigm debugging and ensures functional correctness before final deployment.
• To introduce a new similarity score metric for quantifying layer-wise consistency across software, HLS design, and FPGA hardware implementations.

Proposed method

• The 2L-3W methodology performs two levels of verification: (1) software-level verification of DLA inference and (2) hardware-level verification of the HLS-generated RTL design.
• It implements three-way co-verification by comparing layer-by-layer outputs across three paradigms: Caffe (software), Vivado HLS (design), and PYNQ FPGA (hardware).
• An automated Python script is used to compute a layer-wise similarity score between corresponding outputs from the three platforms, using mean squared error or normalized correlation.
• The method supports incremental debugging by identifying specific layers with low similarity scores, enabling targeted refinement.
• The framework is applied to LeNet and a Caffe-inspired Cifar-10 DLA, using Caffe for software simulation, Vivado HLS for high-level synthesis, and PYNQ FPGA for hardware deployment.
• The similarity score is computed per layer and used as a quantitative metric to assess correctness and guide optimization during the mapping pipeline.

Experimental results

Research questions

• RQ1 Can a 2-level 3-way co-verification framework effectively validate the functional correctness of DLA mapping across software, hardware design, and deployed FPGA platforms?
• RQ2 How accurately can layer-by-layer outputs from Caffe, HLS, and FPGA be aligned to detect implementation discrepancies during DLA deployment on FPGAs?
• RQ3 To what extent does the proposed similarity score metric enable early detection and localization of errors in the DLA mapping pipeline?
• RQ4 Can the methodology support scalable, automated verification without requiring manual inspection of each layer’s output?
• RQ5 How does bit-width truncation during FPGA deployment affect layer-wise output fidelity, and can the framework quantify this impact?

Key findings

• The 2L-3W co-verification methodology achieved a layer-wise similarity score of 99% between the Caffe software implementation and the Vivado HLS design for both LeNet and Caffe-inspired Cifar-10 DLA.
• In the FPGA deployment stage, similarity scores ranged from 65% to 84% due to bit-width reduction for resource constraints, indicating a trade-off between accuracy and hardware efficiency.
• The framework successfully identified layers with low similarity scores, enabling targeted debugging and refinement during the design phase.
• The proposed similarity score metric proved effective in quantifying implementation correctness and guiding optimization across the DLA mapping pipeline.
• The methodology outperforms prior works by enabling full layer-by-layer co-verification across all three paradigms—software, design, and hardware—unlike prior approaches limited to final prediction or software-only validation.
• The study demonstrates that automated, cross-paradigm verification is feasible and essential for reliable DLA deployment on FPGAs, reducing post-deployment debugging and improving design confidence.