[Paper Review] A Combinational Multi-Kernel Decoder for Polar Codes

Hossein Rezaei, Nandana Rajatheva+1 more|arXiv (Cornell University)|Nov 16, 2022

Error Correcting Code Techniques4 citations

TL;DR

This paper proposes a combinational multi-kernel successive cancellation decoder for polar codes that supports mixed binary (2×2) and ternary (3×3) kernels, enabling flexible block lengths beyond powers of two. The architecture achieves high throughput—812.1 Mbps for N=48—using pure combinational logic to decode an entire codeword in one cycle, reducing dynamic power while supporting online rate assignment and arbitrary kernel sequences.

ABSTRACT

Polar codes have been selected as the channel coding scheme for control channel in the fifth generation (5G) communication system thanks to their capacity achieving characteristics. However, the traditional polar codes support only codes constructed by binary (2x2) kernel which limits the code lengths to powers of 2. Multi-kernel polar codes are proposed to achieve flexible block length. In this paper, the first combinational decoder for multi-kernel polar codes based on successive cancellation algorithm is proposed. The proposed decoder can decode pure-binary and binary-ternary (3x3) mixed polar codes. The architecture is rate-flexible with the capability of online rate assignment and supports any kernel sequences. The FPGA implementation results reveal that for a code of length N = 48, the coded throughput of 812.1 Mbps can be achieved.

Motivation & Objective

• To address the limitation of traditional polar codes restricted to block lengths that are powers of two by enabling flexible code lengths using multi-kernel construction.
• To design a high-throughput, low-power decoder for multi-kernel polar codes using combinational logic instead of sequential logic.
• To support online rate assignment and arbitrary kernel sequences, including mixed binary and ternary kernels, for improved system flexibility.
• To achieve higher coded throughput and lower LUT usage compared to existing multi-kernel decoders while maintaining low power consumption.

Proposed method

• The decoder uses a successive cancellation (SC) algorithm implemented entirely with combinational logic, enabling one-clock-cycle decoding of the entire codeword.
• The architecture supports mixed kernel sequences, including pure-binary and binary-ternary combinations, with kernel order specified at runtime.
• The design employs recursive and feed-forward logic structures to minimize area and power, with complexity analysis based on comparators, adders, and subtractors.
• The decoder uses 5-bit LLR quantization and is implemented in VHDL using Xilinx Vivado 2019.1 for FPGA synthesis and place-and-route.
• Memory is managed via RAM blocks storing LLRs, with register duplication used to meet target clock frequency.
• The design is optimized for low LUT usage by modifying sub-decoder encoding circuits to reduce XOR gate count.

Experimental results

Research questions

• RQ1 Can a combinational decoder architecture achieve high throughput and low power for multi-kernel polar codes with mixed binary and ternary kernels?
• RQ2 How does the proposed decoder’s throughput and resource utilization compare to existing sequential or multi-interface decoders for multi-kernel polar codes?
• RQ3 To what extent does the use of combinational logic reduce dynamic power while maintaining high clock frequency and decoding latency?
• RQ4 Can online rate assignment be efficiently integrated into a multi-kernel polar decoder without sacrificing throughput or area efficiency?

Key findings

• The proposed decoder achieves a coded throughput of 812.1 Mbps for a code of length N=48, outperforming prior combinational decoders by 88.5%.
• For N=48, the decoder achieves 22.4% higher throughput than a combinational shortened code of the same size using a mother code of N′=64.
• The FPGA implementation consumes 29.3% fewer LUTs than a comparable decoder from [17], despite supporting more flexible kernel sequences.
• The decoder uses 5.8% more registers than [17], due to register duplication for timing closure at high clock frequency.
• The complexity of the decoder scales approximately as N log₂N, with 812.1 Mbps throughput at N=48 and 884.6 Mbps at N=64.
• The error-correction performance of the MK code (PC(192,96)) is shown to outperform puncturing and shortening methods, with negligible quantization loss at 5-bit LLR resolution.