[Paper Review] A configurable accelerator for manycores: the Explicitly Many-Processor Approach

János Végh|arXiv (Cornell University)|Jul 6, 2016

Parallel Computing and Optimization Techniques16 references3 citations

TL;DR

This paper introduces the Explicitly Many-Processor Approach (EMPA), a novel processor architecture that enables dynamic, end-user-programmable core collaboration via a supervisor layer. By allowing cores to outsource work to neighboring cores using compiler-provided parallelization hints, EMPA boosts computing throughput up to several dozen times, improves hardware efficiency, simplifies real-time operation, and eliminates the need for complex OS services, all while reducing transistor count and power consumption through explicit, non-hidden parallelism management.

ABSTRACT

A new approach to designing processor accelerators is presented. A new computing model and a special kind of accelerator with dynamic (end-user programmable) architecture is suggested. The new model considers a processor, in which a newly introduced supervisor layer coordinates the job of the cores. The cores have the ability (based on the parallelization information provided by the compiler, and using the help of the supervisor) to outsource part of the job they received to some neighbouring core. The introduced changes essentially and advantageously modify the architecture and operation of the computing systems. The computing throughput drastically increases, the efficiency of the technological implementation (computing performance per logic gates) increases, the non-payload activity for using operating system services decreases, the real-time behavior changes advantageously, and connecting accelerators to the processor greatly simplifies. Here only some details of the architecture and operation of the processor are discussed, the rest is described elsewhere.

Motivation & Objective

• To address the stagnation in single-processor performance growth by rethinking the 70-year-old von Neumann single-processor model.
• To overcome limitations in current many-core systems, including poor configurability, OS overhead, and inefficient resource utilization.
• To enable high-performance execution of single-threaded applications on many-core architectures through a new hardware-software co-design model.
• To simplify processor architecture by eliminating hidden processing units and reducing reliance on operating system services.
• To improve real-time determinism and simplify accelerator integration through a natural, atomic execution model.

Proposed method

• Introduces a supervisor layer that coordinates core collaboration, enabling dynamic job outsourcing between neighboring cores.
• Employs a new execution model where cores operate as atomic processing units (Quasi-Threads, QTs), managed explicitly by the hardware.
• Uses compiler-generated parallelization information to guide core cooperation, allowing the parent core to delegate subtasks to helper cores.
• Employs two modes—FOR and SUMUP—where helper cores are used for vector processing, with core utilization optimized via dynamic allocation.
• Applies a core utilization efficiency metric (α_eff) and speedup (S_k) to evaluate performance gains across varying vector lengths.
• Eliminates context switching and OS intervention by making QTs atomic and self-contained, reducing software complexity.

Experimental results

Research questions

• RQ1 Can a new processor model that explicitly manages multiple cores improve performance beyond the limits of traditional single-processor and many-core designs?
• RQ2 How can core collaboration be made programmable and efficient without relying on hidden or speculative processing units?
• RQ3 To what extent can the Explicitly Many-Processor Approach reduce OS overhead and improve real-time determinism in embedded and high-performance systems?
• RQ4 What performance gains are achievable in single-threaded applications when cores are dynamically coordinated for mass data processing?
• RQ5 How does the EMPA model simplify accelerator integration and reduce hardware complexity compared to conventional many-core systems?

Key findings

• The EMPA architecture increases computing throughput by up to several dozen times, especially in data-parallel workloads such as vector sum operations.
• Core utilization efficiency (α_eff) reaches up to 1.0 for long vectors in SUMUP mode, indicating near-optimal use of helper cores.
• Speedup (S_k) saturates at 31 cores (1 parent + 30 helpers), with performance gains maintained even for arbitrarily long vectors due to core recycling.
• The approach reduces the need for operating system services, eliminating context switching and simplifying real-time behavior by making QTs atomic and self-contained.
• The architecture eliminates superfluous logic for managing hidden processing units, reducing transistor count and power consumption.
• Accelerators can be easily connected to the EMPA processor via a standardized interface, as the processor natively supports data and signal exchange with external circuits.