[Paper Review] A novel 4D fast track finding system using precise space and time information of the hit

N. Néri, M. Petruzzo|arXiv (Cornell University)|Dec 30, 2015

CCD and CMOS Imaging Sensors4 references3 citations

TL;DR

This paper proposes a novel 4D fast track finding system that leverages precise space and time information from silicon pixel hits to enable real-time reconstruction of charged particle trajectories with picosecond time resolution. Using a massively parallel, pipelined FPGA implementation of a 4D artificial retina algorithm, the system suppresses out-of-time background hits and achieves sub-microsecond latency, improving tracking performance under high pile-up conditions typical of future high-luminosity LHC experiments.

ABSTRACT

We propose a novel fast track finding system capable of reconstructing four dimensional particle trajectories in real time using precise space and time information of the hits. Recent developments in silicon pixel detectors achieved 150 ps time resolution and intense R&D is in progress to improve the timing performance, aiming at 10 ps. The use of the precise space and time information allows the suppression of background hits not compatible with the time of passage of the particle and the determination of its time evolution. The fast track finding device that we are proposing is based on a massively parallel algorithm implemented in commercial field-programmable gate array using a pipelined architecture. We describe the algorithm and its implementation for a tracking system prototype based on 8 planes of silicon sensors used as a case study. According to simulations the suppression of noise hits is effective in reducing fake track combinations and improving real-time track reconstruction in presence of background hits. The system provides offline-like tracks with sub-microsecond latency and it is capable to determine the time of the track with picosecond resolution assuming 10 ps resolution for the hits.

Motivation & Objective

• To address the challenge of increasing pile-up at the HL-LHC, where up to 140 primary interactions occur per bunch crossing, by improving background rejection in real-time track reconstruction.
• To leverage emerging silicon pixel detectors with sub-100 ps time resolution (down to 10 ps) to add a fourth dimension—time—for discriminating signal from background hits.
• To develop a low-latency, real-time tracking system suitable for integration into the first-level trigger chain of high-energy physics experiments.
• To demonstrate that incorporating time information into the artificial retina algorithm significantly enhances track reconstruction efficiency and reduces fake combinations under high noise conditions.

Proposed method

• The system implements a 4D artificial retina algorithm that extends the traditional 3D spatial track parameter space with time, using track time hypotheses at t₀−ΔT, t₀, and t₀+ΔT for each hit.
• Each processing engine evaluates spatial and temporal Gaussian weight responses: exp(−s²ijk/2σ²) for spatial distance and exp(−t²ijk/2σ²t) for time deviation, combined via DSP blocks in an FPGA.
• A modified switch module routes hits to appropriate engines using look-up tables (LUTs) based on spatial coordinates, with minimal latency and no change to routing logic.
• The track fitter module reconstructs final track parameters (x₊, x₋) by interpolating weight values around local maxima in the response grid.
• The architecture uses a pipelined, massively parallel FPGA design (Xilinx Kintex-7) with a total latency of less than 100 time units (500 ns at 200 MHz), enabling sub-microsecond response.
• The system shares a single LUT for exponentiation operations and uses a 3-cycle hold signal to manage data flow, ensuring stable processing under high data rates.

Experimental results

Research questions

• RQ1 Can precise time information (10 ps resolution) be effectively used to suppress background hits not synchronized with the expected particle passage time?
• RQ2 How does the integration of time as a fourth dimension improve track reconstruction performance in high-pile-up environments?
• RQ3 What is the latency and resource overhead of extending a 3D artificial retina algorithm to 4D with time-resolved hits in an FPGA-based real-time system?
• RQ4 Can a pipelined, massively parallel FPGA architecture achieve sub-microsecond track reconstruction with picosecond time resolution?

Key findings

• The 4D artificial retina algorithm successfully suppresses out-of-time background hits by exploiting time consistency, significantly reducing fake track combinations in simulations.
• The system achieves sub-microsecond latency (under 500 ns at 200 MHz clock) with a total of less than 100 time units, enabling real-time operation suitable for first-level trigger applications.
• The implementation in a Xilinx Kintex-7 FPGA incurs only a 10% increase in FPGA resources compared to the 3D spatial-only version, demonstrating low area overhead.
• The system determines the time of the track at the origin with picosecond resolution, assuming 10 ps time resolution for the input hits.
• The algorithm maintains high tracking performance even under high noise conditions, with improved signal-to-background discrimination via the 4D parameter space.
• The use of shared LUTs and pipelined DSP blocks enables efficient computation with minimal resource usage and low latency.