[Paper Review] A software decoder implementation for H.266/VVC video coding standard

Bin Zhu, Shan Liu+9 more|arXiv (Cornell University)|Dec 4, 2020

Video Coding and Compression Technologies2 references4 citations

TL;DR

This paper presents an optimized software decoder for the H.266/VVC video coding standard, leveraging SIMD instruction extensions and multi-level parallelism (data and task) to achieve real-time decoding of 4K 60fps VVC bitstreams on x86 CPUs. The implementation addresses the standard's high computational complexity, demonstrating practical feasibility for real-time deployment despite the significant performance demands of the new coding efficiency.

ABSTRACT

Versatile Video Coding Standard (H.266/VVC) was completed by Joint Video Expert Team (JVET) of ITU-T and ISO/IEC, in July 2020. This new ITU recommendation/international standard is a successor to the well-known H.265/HEVC video coding standard with roughly doubled compression efficiency, but also at the cost of an increased computational complexity. The complexity of H.266/VVC decoder processing modules is studied in this paper. An optimized decoder implementation using SIMD instruction extensions and additional parallel processing including data and task level parallelism is presented, which can achieve real-time decoding of 4K 60fps VVC bitstreams on an x86 based CPU.

Motivation & Objective

• To address the high computational complexity of the newly standardized H.266/VVC video coding format.
• To develop a practical software decoder capable of real-time decoding for high-resolution video streams.
• To evaluate and optimize decoder processing modules for performance on general-purpose x86 CPUs.
• To enable efficient deployment of H.266/VVC by demonstrating real-time decoding using software-only techniques.

Proposed method

• The decoder implementation uses SIMD instruction extensions to accelerate data-parallel operations in core video decoding processes.
• Task-level parallelism is applied to distribute decoding tasks across multiple CPU cores.
• Data-level parallelism is exploited within SIMD units to process multiple samples simultaneously.
• The design integrates both data and task-level parallelism to maximize throughput on modern x86 architectures.
• The implementation targets the full H.266/VVC decoding pipeline, including entropy decoding, inverse transforms, and sample adaptive offset.
• Optimizations are applied to critical modules such as motion compensation, transform, and loop filtering to reduce latency and improve performance.

Experimental results

Research questions

• RQ1 Can a software-only decoder achieve real-time decoding of 4K 60fps H.266/VVC bitstreams on commodity x86 CPUs?
• RQ2 How effective are SIMD and task-level parallelism in mitigating the high computational complexity of H.266/VVC?
• RQ3 What are the performance bottlenecks in H.266/VVC decoder processing modules, and how can they be optimized?
• RQ4 To what extent can parallel processing and instruction-level parallelism improve decoding throughput for high-efficiency video coding?

Key findings

• The proposed decoder achieves real-time decoding of 4K 60fps H.266/VVC bitstreams on a standard x86-based CPU.
• The use of SIMD instruction extensions significantly accelerates data-parallel operations in the decoding pipeline.
• Combined data and task-level parallelism effectively reduces decoding latency and improves throughput.
• The optimized implementation demonstrates that software-based decoding of H.266/VVC is feasible on general-purpose hardware.
• The study identifies key computational bottlenecks in H.266/VVC decoding and provides targeted optimization strategies.