[Paper Review] Accelerating Implicit Finite Difference Schemes Using a Hardware Optimised Implementation of the Thomas Algorithm for FPGAs

Samuel Palmer, David B. Thomas|arXiv (Cornell University)|Feb 20, 2014

Matrix Theory and Algorithms9 references3 citations

TL;DR

This paper presents a hardware-optimized Thomas algorithm implemented on FPGAs to accelerate implicit finite difference schemes, reducing arithmetic operations from 8N to 5N and minimizing memory overhead to just 2N-length vectors. The design enables parallel solution of multiple tridiagonal systems, significantly improving performance for applications like financial derivatives pricing.

ABSTRACT

The design and implementation of the Thomas algorithm optimised for hardware acceleration on an FPGA is presented. The hardware based algorithm combined with custom data flow and low level parallelism available in an FPGA reduces the overall complexity from 8N down to 5N arithmetic operations, and combined with a data streaming interface reduces memory overheads to only 2 N-length vectors per N-tridiagonal system to be solved. The Thomas Core developed allows for multiple tridiagonal systems to be solved in parallel, giving potential use for solving multiple implicit finite difference schemes or accelerating higher dimensional alternating-direction-implicit schemes used in financial derivatives pricing. This paper also discusses the limitations arising from the fixed-point arithmetic used in the design and how the resultant rounding errors can be controlled to meet a specified tolerance level.

Motivation & Objective

• To reduce computational complexity in solving tridiagonal systems arising in implicit finite difference schemes.
• To minimize memory overhead in hardware-accelerated tridiagonal solvers using FPGA-specific data flow.
• To enable parallel execution of multiple tridiagonal systems for higher-dimensional problems.
• To manage fixed-point arithmetic errors in hardware implementations to meet user-specified tolerance levels.

Proposed method

• Designing a custom Thomas algorithm optimized for FPGA architecture to exploit low-level parallelism.
• Implementing a data streaming interface to reduce memory access and storage requirements to 2N-length vectors per system.
• Using fixed-point arithmetic with controlled rounding to maintain numerical accuracy under hardware constraints.
• Structuring the core to solve multiple tridiagonal systems in parallel, supporting multi-dimensional schemes.
• Applying pipelined execution and hardware-level optimization to reduce arithmetic operations from 8N to 5N.

Experimental results

Research questions

• RQ1 How can the Thomas algorithm be restructured to minimize arithmetic operations in an FPGA-accelerated setting?
• RQ2 What memory overhead is achievable with a streaming data interface in hardware-accelerated tridiagonal solvers?
• RQ3 To what extent can multiple tridiagonal systems be solved in parallel on an FPGA to accelerate higher-dimensional schemes?
• RQ4 How can fixed-point arithmetic errors be bounded to meet a specified tolerance in hardware implementations?

Key findings

• The hardware-optimized Thomas algorithm reduces arithmetic operations from 8N to 5N, significantly improving computational efficiency.
• Memory overhead is minimized to only 2N-length vectors per tridiagonal system, enabling efficient on-chip storage.
• The design supports parallel execution of multiple tridiagonal systems, enabling acceleration of multi-dimensional alternating-direction-implicit schemes.
• Fixed-point arithmetic errors are controlled through rounding strategies to meet user-defined tolerance levels.