[Paper Review] Accelerating Iterative SpMV for Discrete Logarithm Problem Using GPUs

Hamza Jeljeli|arXiv (Cornell University)|Sep 25, 2012

Cryptography and Data Security21 references7 citations

TL;DR

This paper proposes an optimized GPU-accelerated SpMV kernel for solving large sparse linear systems arising in the discrete logarithm problem (DLP) over large finite fields, using CSR-V format with RNS arithmetic and GPU-specific optimizations like texture caching, coefficient reordering, and data compression. The implementation achieved a 5.5x speedup over CPU AVX2 and enabled solving DLP in GF(2^619) and GF(2^809).

ABSTRACT

In the context of cryptanalysis, computing discrete logarithms in large cyclic groups using index-calculus-based methods, such as the number field sieve or the function field sieve, requires solving large sparse systems of linear equations modulo the group order. Most of the fast algorithms used to solve such systems --- e.g., the conjugate gradient or the Lanczos and Wiedemann algorithms --- iterate a product of the corresponding sparse matrix with a vector (SpMV). This central operation can be accelerated on GPUs using specific computing models and addressing patterns, which increase the arithmetic intensity while reducing irregular memory accesses. In this work, we investigate the implementation of SpMV kernels on NVIDIA GPUs, for several representations of the sparse matrix in memory. We explore the use of Residue Number System (RNS) arithmetic to accelerate modular operations. We target linear systems arising when attacking the discrete logarithm problem on groups of size 100 to 1000 bits, which includes the relevant range for current cryptanalytic computations. The proposed SpMV implementation contributed to solving the discrete logarithm problem in GF($2^{619}$) and GF($2^{809}$) using the FFS algorithm.

Motivation & Objective

• Accelerate the iterative sparse-matrix-vector (SpMV) multiplication step in solving large sparse linear systems for the discrete logarithm problem (DLP) in finite fields.
• Address the performance bottleneck in index-calculus algorithms like Function Field Sieve (FFS), where SpMV dominates computational time.
• Optimize SpMV for NVIDIA GPUs by adapting data structures and arithmetic to exploit GPU memory hierarchy and parallelism.
• Enable practical solution of DLP in large finite fields (100–1000 bits), including GF(2^619) and GF(2^809), by accelerating the linear algebra phase.
• Evaluate and compare multiple sparse matrix formats and GPU kernel optimizations to identify the most efficient configuration for DLP-relevant matrices.

Proposed method

• Implement SpMV kernels using the CSR-V (Compressed Sparse Row with Vectorized values) format, which groups rows per warp to improve occupancy and reduce launch overhead.
• Apply texture memory binding to improve global memory coalescing and reduce latency for irregular memory access patterns in sparse matrices.
• Reorder non-zero coefficients per row by type (+1, -1, positive, negative) to minimize branch divergence and improve warp-level execution efficiency.
• Compress the values array by replacing repeated ±1 coefficients with run-length counts, reducing memory traffic by over 10x.
• Permute matrix rows to balance workloads across warps and maximize GPU occupancy, improving resource utilization.
• Use Residue Number System (RNS) arithmetic to enable independent modular operations, enhancing parallelism on GPU.

Experimental results

Research questions

• RQ1 How can SpMV performance be maximized on GPUs for sparse matrices arising in DLP computations over large finite fields?
• RQ2 Which sparse matrix format (e.g., CSR-V, SLCOO) provides the best trade-off between memory access efficiency and computational throughput on GPU?
• RQ3 To what extent do GPU-specific optimizations—such as texture caching, coefficient reordering, and data compression—improve SpMV performance for DLP matrices?
• RQ4 How does RNS arithmetic contribute to parallelism and performance in modular arithmetic on GPU?
• RQ5 What is the achievable speedup of GPU-optimized SpMV over state-of-the-art CPU implementations for DLP-relevant sparse systems?

Key findings

• The CSR-V kernel achieved the highest performance, with a 5.5x speedup over the fastest CPU AVX2 implementation (21.2 GFLOP/s vs. 57.6 GFLOP/s on GPU).
• Texture caching improved global memory load efficiency from 47.2% to 84%, reducing SpMV delay by 30%.
• Coefficient reordering reduced branch divergence from 36.7% to 12.9%, contributing to a 5% performance gain.
• Data compression reduced the number of executed instructions by 1.4% (from 5.8×10⁸ to 5.72×10⁸), yielding an 11% speedup.
• Row permutation increased occupancy from 74.9% to 81.8%, improving performance by 1%.
• The optimized GPU SpMV implementation contributed to solving the discrete logarithm problem in GF(2^619) and GF(2^809), demonstrating practical feasibility for large-scale DLP cryptanalysis.