[Paper Review] AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence

Yunhe Wang, Mingqiang Huang+5 more|arXiv (Cornell University)|Jan 25, 2021

Advanced Memory and Neural Computing40 references22 citations

TL;DR

This paper proposes AdderNet, a novel neural network architecture that replaces traditional multiplication-based convolutions with addition-only operations, enabling significant energy and hardware efficiency. By combining int8/int16 quantization with a minimalist FPGA-accelerated hardware design, AdderNet achieves up to 77.9% lower power consumption and 67.6% less logic resource usage than CNNs, while maintaining comparable accuracy on ImageNet and CIFAR-10 benchmarks.

ABSTRACT

Convolutional neural networks (CNN) have been widely used for boosting the performance of many machine intelligence tasks. However, the CNN models are usually computationally intensive and energy consuming, since they are often designed with numerous multiply-operations and considerable parameters for the accuracy reason. Thus, it is difficult to directly apply them in the resource-constrained environments such as 'Internet of Things' (IoT) devices and smart phones. To reduce the computational complexity and energy burden, here we present a novel minimalist hardware architecture using adder convolutional neural network (AdderNet), in which the original convolution is replaced by adder kernel using only additions. To maximally excavate the potential energy consumption, we explore the low-bit quantization algorithm for AdderNet with shared-scaling-factor method, and we design both specific and general-purpose hardware accelerators for AdderNet. Experimental results show that the adder kernel with int8/int16 quantization also exhibits high performance, meanwhile consuming much less resources (theoretically ~81% off). In addition, we deploy the quantized AdderNet on FPGA (Field Programmable Gate Array) platform. The whole AdderNet can practically achieve 16% enhancement in speed, 67.6%-71.4% decrease in logic resource utilization and 47.85%-77.9% decrease in power consumption compared to CNN under the same circuit architecture. With a comprehensive comparison on the performance, power consumption, hardware resource consumption and network generalization capability, we conclude the AdderNet is able to surpass all the other competitors including the classical CNN, novel memristor-network, XNOR-Net and the shift-kernel based network, indicating its great potential in future high performance and energy-efficient artificial intelligence applications.

Motivation & Objective

• To address the high energy and computational cost of deep learning models in resource-constrained environments like IoT and mobile devices.
• To reduce reliance on multiply-accumulate (MAC) operations, which are power-intensive in conventional CNNs.
• To design a minimalist, energy-efficient hardware accelerator tailored for addition-based neural networks.
• To achieve high accuracy with low-precision quantization (int8/int16) in an addition-only computation framework.
• To demonstrate superior performance and efficiency compared to existing alternatives, including XNOR-Net, memristor networks, and shift-based networks.

Proposed method

• Replace standard convolutional layers with adder kernels that compute output as the sum of absolute differences between input feature maps and learnable kernel weights.
• Implement a shared-scaling-factor quantization method to enable low-bit (int8/int16) inference while preserving model accuracy.
• Design a dedicated FPGA-based hardware accelerator using a 2A (two-adder) architecture for efficient addition-based computation.
• Optimize the hardware design for minimal logic area and power consumption by eliminating multipliers and reducing complex logic.
• Deploy and benchmark AdderNet on FPGA under identical circuit constraints as standard CNNs to enable fair comparison.
• Train and fine-tune AdderNet using standard backpropagation with a differentiable approximation of the absolute difference operation.

Experimental results

Research questions

• RQ1 Can an addition-only neural network architecture achieve comparable accuracy to standard CNNs while drastically reducing computational energy?
• RQ2 How does low-bit quantization (int8/int16) affect the performance and energy efficiency of adder-based networks?
• RQ3 What is the hardware resource and power consumption overhead of implementing AdderNet on FPGA compared to conventional CNNs?
• RQ4 How does AdderNet compare in efficiency and accuracy to other state-of-the-art energy-efficient networks like XNOR-Net, DeepShift, and memristor-based networks?
• RQ5 Can the shared-scaling-factor quantization method effectively preserve model accuracy at low bit-widths without introducing significant degradation?

Key findings

• AdderNet with int8/int16 quantization maintains high accuracy, achieving 76.6% Top-1 accuracy on ImageNet-1K and 91.78% Top-1 accuracy on CIFAR-10, comparable to full-precision CNNs.
• On FPGA, AdderNet achieves 16% higher inference speed, 67.6%–71.4% reduction in logic resource utilization, and 47.85%–77.9% reduction in power consumption compared to equivalent CNNs.
• The 2A hardware architecture enables efficient addition computation with lower circuit complexity than comparators, reducing area and power overhead.
• AdderNet outperforms XNOR-Net, DeepShift, memristor networks, and shift-kernel networks in terms of energy efficiency, hardware footprint, and accuracy retention under low-precision settings.
• The shared-scaling-factor quantization method enables stable performance at int8 and int16, though accuracy degrades significantly at 4-bit precision due to information loss.
• Comprehensive benchmarking confirms AdderNet’s superiority in balancing performance, energy efficiency, and hardware resource usage across diverse edge AI applications.