[Paper Review] An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm

Keisuke Sugiura, Hiroki Matsutani|arXiv (Cornell University)|May 29, 2020

Robotics and Sensor-Based Localization27 references4 citations

TL;DR

This paper presents a resource-efficient FPGA-based accelerator for 2D LiDAR SLAM using GMapping, leveraging parallel scan matching across particles and map compression to achieve 5.31–8.75× speedup in scan matching and 3.72–5.10× overall throughput improvement, with only 44% FPGA resource utilization on a Pynq-Z2 board.

ABSTRACT

An efficient hardware implementation for Simultaneous Localization and Mapping (SLAM) methods is of necessity for mobile autonomous robots with limited computational resources. In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods. Scan matching is a process of correcting a robot pose by aligning the latest LiDAR measurements with an occupancy grid map, which encodes the information about the surrounding environment. We exploit an inherent parallelism in the Rao-Blackwellized Particle Filter (RBPF) based algorithms to perform scan matching computations for multiple particles in parallel. In the proposed design, several techniques are employed to reduce the resource utilization and to achieve the maximum throughput. Experimental results using the benchmark datasets show that the scan matching is accelerated by 5.31-8.75x and the overall throughput is improved by 3.72-5.10x without seriously degrading the quality of the final outputs. Furthermore, our proposed IP core requires only 44% of the total resources available in the TUL Pynq-Z2 FPGA board, thus facilitating the realization of SLAM applications on indoor mobile robots.

Motivation & Objective

• Address the high computational cost of 2D LiDAR SLAM in resource-constrained mobile robots.
• Overcome the bottleneck of scan matching in RBPF-based SLAM algorithms like GMapping.
• Design a lightweight, high-throughput FPGA accelerator that maintains accuracy while minimizing resource usage.
• Enable real-time SLAM on low-power, embedded platforms such as the Pynq-Z2 FPGA board.

Proposed method

• Exploited inherent parallelism in Rao-Blackwellized Particle Filter (RBPF) to perform scan matching for multiple particles simultaneously on FPGA.
• Applied map compression via binarization and local map regions to reduce BRAM usage and improve data access efficiency.
• Used fixed-point arithmetic with precomputed lookup tables to eliminate costly floating-point operations in coordinate transformations.
• Optimized dataflow to minimize off-chip memory access and reduce latency in scan matching computations.
• Implemented a pipelined architecture for the scan matcher IP core targeting Xilinx Zynq ZC7Z020 FPGA at 100 MHz.
• Balanced parallelization degree (2 particles) to stay within BRAM and LUT constraints while maximizing throughput.

Experimental results

Research questions

• RQ1 Can FPGA-based acceleration achieve significant speedup in 2D LiDAR SLAM scan matching without degrading accuracy?
• RQ2 How effective is map compression (binarization + local maps) in reducing FPGA resource usage for SLAM?
• RQ3 To what extent does fixed-point arithmetic and lookup tables preserve accuracy in scan matching compared to floating-point software?
• RQ4 What is the achievable throughput and resource utilization when accelerating GMapping on a low-power FPGA platform?
• RQ5 Can the hardware-accelerated SLAM maintain topological and geometric consistency with software baseline?

Key findings

• The FPGA accelerator achieved 5.31–8.75× speedup in scan matching computation across benchmark datasets.
• Overall system throughput improved by 3.72–5.10× compared to the software-only CPU implementation.
• The final map quality and trajectory accuracy were preserved, with only minor differences in pose estimation (e.g., 0.0712±0.127 m RMSE on ACES dataset).
• The design consumed only 43.6% of available BRAM and 43.7% of LUTs on the Pynq-Z2 FPGA, indicating high resource efficiency.
• Power consumption remained at 2.9 W, matching the software baseline, while achieving significantly faster execution.
• The implementation supports future scalability, with remaining resources allowing for increased parallelization (e.g., 4 particles) or offloading of additional algorithmic components.