[Paper Review] An FPGA cached sparse matrix vector product (SpMV) for unstructured computational fluid dynamics simulations

Guillermo Oyarzun, Daniel Peyrolon+2 more|arXiv (Cornell University)|Jul 24, 2021

Parallel Computing and Optimization Techniques14 references4 citations

TL;DR

This paper proposes an FPGA-based cached sparse matrix-vector multiplication (SpMV) for unstructured computational fluid dynamics (CFD) simulations, using a circular list cache to maximize reuse of the input vector. By leveraging problem-specific sparsity patterns and optimizing memory access via BRAM-based caching, the approach achieves up to 16× speedup over a naive FPGA implementation and 12× over a full-vector BRAM-caching library.

ABSTRACT

Field Programmable Gate Arrays generate algorithmic specific architectures that improve the code's FLOP per watt ratio. Such devices are re-gaining interest due to the rise of new tools that facilitate their programming, such as OmpSs. The computational fluid dynamics community is always investigating new architectures that can improve its algorithm's performance. Commonly, those algorithms have a low arithmetic intensity and only reach a small percentage of the peak performance. The sparse matrix-vector multiplication is one of the most time-consuming operations on unstructured simulations. The matrix's sparsity pattern determines the indirect memory accesses of the multiplying vector. This data path is hard to predict, making traditional implementations fail. In this work, we present an FPGA architecture that maximizes the vector's re-usability by introducing a cache-like architecture. The cache is implemented as a circular list that maintains the BRAM vector components while needed. Following this strategy, up to 16 times of acceleration is obtained compared to a naive implementation of the algorithm.

Motivation & Objective

• Address the low arithmetic intensity and poor memory access patterns in unstructured CFD simulations that limit performance on CPUs and GPUs.
• Overcome the challenge of indirect, unpredictable memory accesses in SpMV for unstructured meshes, which hinder efficient hardware mapping.
• Improve energy efficiency and performance in HPC workloads by exploiting FPGA reconfigurability for problem-specific SpMV acceleration.
• Develop a cache-aware SpMV architecture that maximizes reuse of the input vector while minimizing off-chip memory bandwidth.
• Demonstrate significant performance gains over both naive FPGA implementations and existing open-source SpMV libraries targeting FPGAs.

Proposed method

• Implement a cache-like structure using a circular list in block RAM (BRAM) to store frequently accessed elements of the input vector.
• Use a sliced ELLPACK format with column-wise ordering to store the sparse matrix, enabling efficient memory access patterns.
• Apply a preprocessing step to identify and prioritize vector elements with high reuse potential, reducing cache misses.
• Optimize the cache size (16,384 entries) and block size (512 rows per slice) to balance resource usage and performance on the FPGA.
• Integrate the SpMV kernel into an OmpSs-based programming model to simplify high-level coding and enable automatic HLS compilation via Vivado HLS.
• Use a directive-based programming model to map the algorithm to FPGA hardware with minimal low-level hardware design expertise.

Experimental results

Research questions

• RQ1 How can FPGA-based SpMV be optimized for unstructured CFD simulations with low arithmetic intensity and irregular memory access patterns?
• RQ2 To what extent can a circular list cache in BRAM improve data reuse and reduce off-chip memory bandwidth in SpMV kernels?
• RQ3 How does the proposed cache-based SpMV compare in performance and resource usage to a naive FPGA implementation without caching?
• RQ4 Can the proposed approach outperform existing open-source FPGA SpMV libraries that cache the entire input vector in BRAM?
• RQ5 What is the maximum achievable speedup for SpMV in unstructured CFD matrices using FPGA-specific caching and data layout optimizations?

Key findings

• The proposed cache-based SpMV achieves up to 16.41× speedup over a naive FPGA implementation on matrices ranging from 50K to 800K rows.
• The speedup increases with matrix size due to greater spatial and temporal locality in indirect memory accesses for larger, sparser matrices.
• Compared to an open-source library that caches the entire input vector in BRAM, the proposed method achieves up to 12.35× speedup on the same test matrices.
• The cache SpMV design supports only four concurrent instances due to BRAM constraints, while the naive implementation supports up to 32, highlighting a trade-off between performance and resource utilization.
• The optimal configuration uses a cache size of 16,384 entries (32 words) and a block size of 512 rows per slice, balancing performance and resource efficiency.
• The method demonstrates strong scalability in performance per watt, making it suitable for energy-constrained exascale HPC workloads in CFD.