[Paper Review] Architecture-Aware, High Performance Transaction for Persistent Memory

Kai Wu, Jie Ren+1 more|arXiv (Cornell University)|Mar 14, 2019

Advanced Data Storage Technologies47 references4 citations

TL;DR

This paper proposes Archapt, an architecture-aware transaction system for persistent memory that reduces cache-line flushing overhead by leveraging hardware caching behavior and coalescing low-dirtiness cache lines. By estimating cache residency and using checksum-based consistency recovery, Archapt reduces cache flushing by 66% and improves throughput by 19% on average compared to PMDK and Mnemosyne baselines.

ABSTRACT

Byte-addressable non-volatile main memory (NVM) demands transactional mechanisms to access and manipulate data on NVM atomically. Those transaction mechanisms often employ a logging mechanism (undo logging or redo logging). However, the logging mechanisms can bring large runtime overhead (8%-49% in our evaluation), and 41%-78% of the overhead attributes to the frequent cache-line flushing. Such large overhead significantly diminishes the performance benefits offered by NVM. In this paper, we introduce a new method to reduce the overhead of cache-line flushing for logging-based transactions. Different from the traditional method that works at the program level and leverages program semantics to reduce the logging overhead, we introduce architecture awareness. In particular, we do not flush certain cache blocks, as long as they are estimated to be eliminated out of the cache because of the hardware caching mechanism (e.g., the cache replacement algorithm). Furthermore, we coalesce those cache blocks with low dirtiness to improve the efficiency of cache-line flushing. We implement an architecture-aware, high performance transaction runtime system for persistent memory, Archapt. Our results show that comparing with an undo logging (PMDK) and a redo logging (Mnemosyne), Archapt reduces cache-line flushing by 66% and improves system throughput by 19% on average (42% at most). Our crash tests with four hardware caching policies show that Archapt provides a strong guarantee on crash consistency.

Motivation & Objective

• Address the high runtime overhead of logging-based transactions in persistent memory, particularly due to frequent cache-line flushing.
• Reduce performance degradation caused by explicit cache-line flush instructions in transactional systems.
• Maintain strong crash consistency while minimizing cache-line flushing through architecture-aware optimizations.
• Improve efficiency of cache-line flushing by coalescing low-dirtiness cache blocks.
• Provide a lightweight, software-only mechanism to estimate cache residency without hardware modifications.

Proposed method

• Estimate whether dirty cache blocks of persistent objects remain in the cache using a software approximation of hardware cache replacement policies (e.g., LRU).
• Skip explicit cache-line flushing for blocks that are likely to be evicted by the hardware cache replacement mechanism.
• Coalesce cache blocks with low dirtiness (average 49%) to reduce the number of full-line flushes and improve memory bandwidth efficiency.
• Use a checksum mechanism to detect and correct inconsistent persistent objects after crashes, ensuring crash consistency.
• Integrate the optimization into a transaction runtime system (Archapt) that supports both undo and redo logging mechanisms.
• Leverage existing hardware caching mechanisms implicitly, avoiding the need for explicit flush instructions when eviction is imminent.

Experimental results

Research questions

• RQ1 Can architecture-aware estimation of cache residency reduce the number of explicit cache-line flushes in persistent memory transactions?
• RQ2 How effective is coalescing low-dirtiness cache blocks in improving the efficiency of cache-line flushing?
• RQ3 Can a software-based approximation of hardware cache behavior maintain crash consistency while skipping flushes?
• RQ4 What is the performance impact of skipping cache-line flushes on system throughput and latency?
• RQ5 How robust is the checksum-based inconsistency detection and correction mechanism under diverse hardware caching policies?

Key findings

• Archapt reduces cache-line flushing by 66% on average compared to baseline undo (PMDK) and redo (Mnemosyne) logging mechanisms.
• System throughput improves by 19% on average (up to 42%) across TPC-C, YCSB, and OLTP-bench workloads.
• The checksum mechanism successfully detects and corrects all inconsistent persistent objects in 100 crash tests across four hardware caching policies.
• Only up to a few hundred inconsistent persistent objects were detected per 100 crash tests, even with billions of updates, indicating high reliability.
• The average dirtiness of flushed cache lines is 49% for both undo and redo logging, confirming that coalescing low-dirtiness blocks significantly improves flushing efficiency.
• The approach maintains strong crash consistency without relaxing write ordering constraints, unlike prior work that relaxes persistency ordering for performance.