[Paper Review] Architecture for real time continuous sorting on large width data volume for fpga based applications

Rourab Paul, Suman Sau+1 more|arXiv (Cornell University)|Jun 7, 2012

Parallel Computing and Optimization Techniques6 references3 citations

TL;DR

This paper presents a scalable FPGA-based architecture for real-time continuous sorting of high-width data streams using a modified counting sort algorithm. By enabling in-stream data processing without prior storage, the design achieves constant-time sorting regardless of data length, demonstrating superior resource efficiency and performance on a Spartan 3E FPGA compared to prior approaches.

ABSTRACT

In engineering applications sorting is an important and widely studied problem where execution speed and resources used for computation are of extreme importance, especially if we think about real time data processing. Most of the traditional sorting techniques compute the process after receiving all of the data and hence the process needs large amount of resources for data storage. So, suitable design strategy needs to be adopted if we wish to sort a large amount of data in real time, which essential means higher speed of process execution and utilization of fewer resources in most of the cases. This paper proposes a single chip scalable architecture based on Field Programmable Gate Array(FPGA), for a modified counting sort algorithm where data acquisition and sorting is being done in real time scenario. Our design promises to work efficiently, where data can be accepted in the run time scenario without any need of prior storage of data and also the execution speed of our algorithm is invariant to the length of the data stream. The proposed design is implemented and verified on Spartan 3E(XC3S500E-FG320) FPGA system. The results prove that our design is better in terms of some of the design parameters compared to the existing research works.

Motivation & Objective

• Address the challenge of real-time sorting in high-throughput engineering applications where traditional sorting requires full data buffering.
• Overcome resource inefficiency in conventional sorting by eliminating the need for prior data storage.
• Enable continuous, real-time sorting of large-width data streams on a single FPGA chip.
• Design a scalable architecture that maintains constant sorting speed regardless of data stream length.
• Optimize resource usage and execution speed for embedded FPGA-based systems in real-time processing environments.

Proposed method

• Proposes a modified counting sort algorithm tailored for streaming data, avoiding full data storage.
• Introduces a hardware architecture that processes and sorts data as it arrives, enabling continuous operation.
• Uses a single FPGA (Spartan 3E XC3S500E-FG320) to implement the sorting logic in real time.
• Employs a parallel processing structure to handle high data width efficiently.
• Designs the architecture to be scalable, supporting varying data stream widths.
• Validates the design through implementation and testing on a physical FPGA platform.

Experimental results

Research questions

• RQ1 How can real-time sorting be achieved without storing the entire data set before processing?
• RQ2 What architectural modifications to counting sort enable continuous, low-latency sorting on streaming data?
• RQ3 Can an FPGA-based design maintain constant sorting time regardless of data stream length?
• RQ4 How does the proposed architecture compare to existing solutions in terms of resource usage and throughput?
• RQ5 What is the performance and scalability of the design on a commercial FPGA platform?

Key findings

• The proposed architecture achieves constant sorting time regardless of data stream length, demonstrating invariance to data volume.
• The design eliminates the need for prior data buffering, enabling true real-time processing.
• Implementation on a Spartan 3E FPGA confirms the feasibility and efficiency of the architecture.
• The system shows improved resource utilization compared to existing FPGA-based sorting solutions.
• The architecture is scalable and suitable for high-width data streams in embedded real-time applications.