[Paper Review] AsicBoost - A Speedup for Bitcoin Mining

Yaish, Aviv, Zohar, Aviv|arXiv (Cornell University)|Apr 3, 2016

Blockchain Technology Applications and Security12 citations

TL;DR

AsicBoost is a 20% performance-optimization technique for Bitcoin mining that reuses the SHA-256 message schedule across multiple block header candidates by generating colliding work items. It achieves this by reordering mining loops and sharing Expander 1 computation across multiple mid-states, reducing gate count and cutting energy and cost per gigahash by ~20%.

ABSTRACT

AsicBoost is a method to speed up Bitcoin mining by a factor of approximately 20%. The performance gain is achieved through a high-level optimization of the Bitcoin mining algorithm which allows for drastic reduction in gate count on the mining chip. AsicBoost is applicable to all types of mining hardware and chip designs. This paper presents the idea behind the method and describes the information flow in implementations of AsicBoost.

Motivation & Objective

• To develop a novel algorithmic optimization that improves Bitcoin mining efficiency beyond existing low-level hardware optimizations.
• To reduce the computational overhead of SHA-256 processing in mining ASICs by reusing intermediate results across multiple work items.
• To lower both energy consumption (Joules per Gh) and system cost ($ per Gh/s), thereby improving mining profitability.
• To enable performance gains compatible with existing ASIC design philosophies such as pipelined and non-pipelined cores.
• To demonstrate that the method can be implemented in hardware (ASICs) or software (GPUs), with minimal overhead in memory-rich environments.

Proposed method

• Reorganize the mining loop to iterate over multiple mid-states (from colliding block headers) before updating the nonce, enabling reuse of the Expander 1 function.
• Generate colliding block header candidates by varying only the first chunk (e.g., via free bits in the previous hash or transaction reordering), while keeping the Merkle root or message part constant.
• Share the Expander 1 output across multiple hashing cores (e.g., in a Duo-core or Multi-core design), reducing redundant computation and gate count.
• Implement a Low-Toggle core design where Expander 1 logic toggles only when the nonce or message changes, minimizing dynamic power consumption.
• Preprocess work items in mining software to compute and cache mid-states and messages for colliding candidates before sending them to the ASIC.
• Use message schedule reuse to eliminate the Expander 1 function from the inner loop, reducing the number of high-frequency operations by up to 25%.

Experimental results

Research questions

• RQ1 Can the SHA-256 message schedule be reused across multiple block headers to reduce redundant computation in Bitcoin mining?
• RQ2 What is the maximum performance gain achievable by reordering mining loops and sharing intermediate computation in ASIC designs?
• RQ3 How does AsicBoost’s gate count reduction translate into measurable improvements in energy efficiency and system cost per gigahash?
• RQ4 To what extent is AsicBoost compatible with existing ASIC design methodologies such as pipelined or non-pipelined cores?
• RQ5 Can the performance gains of AsicBoost be achieved in software (e.g., on GPUs) without significant memory or computational overhead?

Key findings

• AsicBoost achieves a performance gain of up to 23.4% when processing 16 colliding work items, with a theoretical maximum gain of 25% if Expander 1 accounts for one-quarter of total computation.
• The method reduces both energy consumption (Joules per Gh) and system cost ($ per Gh/s) by approximately 20%, directly improving mining profitability.
• The performance gain is additive with prior optimizations—previous work estimated a 7% gain from all known optimizations before AsicBoost, making its 20% gain highly significant.
• AsicBoost is compatible with both pipelined and non-pipelined ASIC core designs, enabling broad applicability across existing mining hardware architectures.
• The method can be implemented in software on GPUs with minimal overhead due to random-access memory availability, making it feasible for non-ASIC platforms.
• The Low-Toggle core design reduces dynamic power consumption by limiting Expander 1 toggling frequency to only when the nonce or message changes, preserving energy savings.